MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 114

IC MCU 3MHZ 512 EEPROM 52-PLCC

MC68HC11E1CFN3

Manufacturer Part Number
MC68HC11E1CFN3
Description
IC MCU 3MHZ 512 EEPROM 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
22
Number Of Timers
16 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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Parallel Input/Output (I/O) Ports
6.8 Parallel I/O Control Register
Data Sheet
114
Simple
strobed
mode
Full-input
hand-
shake
mode
Read
PIOC with
STAF = 1
then read
PORTCL
Read
PIOC with
STAF = 1
then read
PORTCL
Sequence
Clearing
STAF
Full handshake modes use port C pins and the STRA and STRB lines. Input and
output handshake modes are supported, and output handshake mode has a
3-stated variation. STRA is an edge-detecting input and STRB is a handshake
output. Control and enable bits are located in the PIOC register.
In full input handshake mode, the MCU asserts STRB to signal an external system
that it is ready to latch data. Port C logic levels are latched into PORTCL when the
STRA line is asserted by the external system. The MCU then negates STRB. The
MCU reasserts STRB after the PORTCL register is read. In this mode, a mix of
latched inputs, static inputs, and static outputs is allowed on port C, differentiated
by the data direction bits and use of the PORTC and PORTCL registers.
In full output handshake mode, the MCU writes data to PORTCL which, in turn,
asserts the STRB output to indicate that data is ready. The external system reads
port C data and asserts the STRA input to acknowledge that data has been
received.
In the 3-state variation of output handshake mode, lines intended as 3-state
handshake outputs are configured as inputs by clearing the corresponding DDRC
bits. The MCU writes data to PORTCL and asserts STRB. The external system
responds by activating the STRA input, which forces the MCU to drive the data in
PORTC out on all of the port C lines. After the trailing edge of the active signal on
STRA, the MCU negates the STRB signal. The 3-state mode variation does not
allow part of port C to be used for static inputs while other port C pins are being
used for handshake outputs. Refer to the
further information.
The parallel handshake functions are available only in the single-chip operating
mode. PIOC is a read/write register except for bit 7, which is read only.
shows a summary of handshake operations.
HNDS
0
1
Freescale Semiconductor, Inc.
For More Information On This Product,
OIN
X
0
Table 6-2. Parallel I/O Control
0 = STRB
active level
1 = STRB
active pulse
Parallel Input/Output (I/O) Ports
Go to: www.freescale.com
PLS
X
0
1
1
0
EGA
6.8 Parallel I/O Control Register
Inputs latched into
PORTCL on any
active edge on
STRA
Inputs latched into
PORTCL on any
active edge on
STRA
Port B
M68HC11E Family — Rev. 5
STRB pulses
on writes
to PORTB
Normal output
port, unaffected
in handshake
modes
MOTOROLA
Table 6-2
Port C
for

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