MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 133

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

8.1 Introduction
8.2 Functional Description
M68HC11E Family — Rev. 5
MOTOROLA
Data Sheet — M68HC11E Family
The serial peripheral interface (SPI), an independent serial communications
subsystem, allows the MCU to communicate synchronously with peripheral
devices, such as:
The SPI is also capable of inter-processor communication in a multiple master
system. The SPI system can be configured as either a master or a slave device.
When configured as a master, data transfer rates can be as high as one-half the
E-clock rate (1.5 Mbits per second for a 3-MHz bus frequency). When configured
as a slave, data transfers can be as fast as the E-clock rate (3 Mbits per second for
a 3-MHz bus frequency).
The central element in the SPI system is the block containing the shift register and
the read data buffer. The system is single buffered in the transmit direction and
double buffered in the receive direction. This means that new data for transmission
cannot be written to the shifter until the previous transfer is complete; however,
received data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial character. As long as the first character is read out of the
read data buffer before the next serial character is ready to be transferred, no
overrun condition occurs. A single MCU register address is used for reading data
from the read data buffer and for writing data to the shifter.
The SPI status block represents the SPI status functions (transfer complete, write
collision, and mode fault) performed by the serial peripheral status register (SPSR).
The SPI control block represents those functions that control the SPI system
through the serial peripheral control register (SPCR).
Refer to
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•
•
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Frequency synthesizers
Liquid crystal display (LCD) drivers
Analog-to-digital (A/D) converter subsystems
Other microprocessors
Freescale Semiconductor, Inc.
Figure
For More Information On This Product,
8-1, which shows the SPI block diagram.
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
Section 8. Serial Peripheral Interface (SPI)
Data Sheet
133