MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 151

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

9.4.2 Timer Compare Force Register
M68HC11E Family — Rev. 5
MOTOROLA
The CFORC register allows forced early compares. FOC[1:5] correspond to the
five output compares. These bits are set for each output compare that is to be
forced. The action taken as a result of a forced compare is the same as if there
were a match between the OCx register and the free-running counter, except that
the corresponding interrupt status flag bits are not set. The forced channels trigger
their programmed pin actions to occur at the next timer count transition after the
write to CFORC.
The CFORC bits should not be used on an output compare function that is
programmed to toggle its output on a successful compare because a normal
compare that occurs immediately before or after the force can result in an
undesirable operation.
FOC[1:5] — Force Output Comparison Bit
Bits [2:0] — Unimplemented
When the FOC bit associated with an output compare circuit is set, the output
compare circuit immediately performs the action it is programmed to do when
an output match occurs.
Always read 0
Address:
Reset:
Read:
Write:
0 = Not affected
1 = Output x action occurs
Freescale Semiconductor, Inc.
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FOC1
Figure 9-12. Timer Compare Force Register (CFORC)
Bit 7
0
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= Unimplemented
FOC2
6
0
Timing System
FOC3
5
0
FOC4
4
0
FOC5
3
0
2
0
Output Compare
1
0
Timing System
Data Sheet
Bit 0
0
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