MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 39

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

M68HC11E Family — Rev. 5
MOTOROLA
$100A
$100B
$100C
$100D
$100E
$1005
$1006
$1007
$1008
$1009
$100F
$1010
$1011
Addr.
Output Compare 1 Mask Register
Output Compare 1 Data Register
Timer Compare Force Register
Timer Input Capture 1 Register
Timer Input Capture 1 Register
Port C Data Direction Register
Port D Data Direction Register
Timer Counter Register High
Timer Counter Register Low
Register Name
Port C Latched Register
Port D Data Register
Port E Data Register
Figure 2-7. Register and Control Bit Assignments (Sheet 2 of 6)
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See page 147.
High (TIC1H)
Low (TIC1L)
(PORTCL)
Reserved
(CFORC)
(PORTD)
(PORTE)
(TCNTH)
(TCNTL)
(DDRC)
(DDRD)
(OC1M)
(OC1D)
Freescale Semiconductor, Inc.
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Reset:
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Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read: Bit 15
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Operating Modes and On-Chip Memory
I = Indeterminate after reset
DDRC7
OC1M7
OC1D7
Bit 15
FOC1
PCL7
Bit 7
Bit 7
Bit 7
PE7
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R
U
0
0
0
0
0
0
0
0
= Unimplemented
DDRC6
OC1M6
OC1D6
Bit 14
Bit 14
FOC2
PCL6
Bit 6
Bit 6
PE6
R
U
6
0
0
0
0
0
0
0
0
DDRC5
DDRD5
OC1M5
OC1D5
Bit 13
Bit 13
FOC3
PCL5
Bit 5
Bit 5
PD5
PE5
R
5
0
0
0
0
0
0
0
I
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
DDRC4
DDRD4
OC1M4
OC1D4
Bit 12
Bit 12
FOC4
PCL4
Bit 4
Bit 4
PD4
PE4
R
R
0
0
0
0
0
0
0
4
I
Operating Modes and On-Chip Memory
= Reserved
DDRC3
DDRD3
OC1M3
OC1D3
Bit 11
Bit 11
FOC5
PCL3
Bit 3
Bit 3
PD3
PE3
R
3
0
0
0
0
0
0
0
I
DDRC2
DDRD2
Bit 10
Bit 10
U = Unaffected
PCL2
Bit 2
Bit 2
PD2
PE2
R
2
0
0
0
0
0
0
0
I
DDRC1
DDRD1
PCL1
Bit 9
Bit 1
Bit 9
Bit 1
PD1
PE1
R
1
0
0
0
0
0
0
0
I
Memory Map
Data Sheet
DDRC0
DDRD0
PCL0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 0
PD0
PE0
R
0
0
0
0
0
0
0
I
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