MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 45

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

2.3.2 Mode Selection
M68HC11E Family — Rev. 5
MOTOROLA
In expanded modes, the ROM/EPROM/OTPROM (if present) is enabled out of
reset and located at the top of the memory map if the ROMON bit in the CONFIG
register is set. ROM or EPROM is enabled out of reset in single-chip and bootstrap
modes, regardless of the state of ROMON.
For devices with 512 bytes of EEPROM, the EEPROM is located at $B600–$B7FF
and has the same read cycle time as the internal ROM. The 512 bytes of EEPROM
cannot be remapped to other locations.
For the MC68HC811E2, EEPROM is located at $F800–$FFFF and can be
remapped to any 4-Kbyte boundary. EEPROM mapping control bits (EE[3:0] in
CONFIG) determine the location of the 2048 bytes of EEPROM and are present
only on the MC68HC811E2. Refer to
a description of the MC68HC811E2 CONFIG register.
EEPROM can be programmed or erased by software and an on-chip charge pump,
allowing EEPROM changes using the single V
The four mode variations are selected by the logic states of the MODA and MODB
pins during reset. The MODA and MODB logic levels determine the logic state of
SMOD and the MDA control bits in the highest priority I-bit interrupt and
miscellaneous (HPRIO) register.
After reset is released, the mode select pins no longer influence the MCU operating
mode. In single-chip operating mode, the MODA pin is connected to a logic level 0.
In expanded mode, MODA is normally connected to V
of 4.7 kΩ. The MODA pin also functions as the load instruction register LIR pin
when the MCU is not in reset. The open-drain active low LIR output pin drives low
during the first E cycle of each instruction. The MODB pin also functions as standby
power input (V
V
Refer to
bits, and the four operating modes.
DD
.
MODB
Freescale Semiconductor, Inc.
1
1
0
0
Table
Input Levels
For More Information On This Product,
at Reset
Operating Modes and On-Chip Memory
STBY
2-1, which is a summary of mode pin operation, the mode control
Go to: www.freescale.com
MODA
Table 2-1. Hardware Mode Select Summary
), which allows RAM contents to be maintained in absence of
0
1
0
1
Special test
Single chip
Expanded
Bootstrap
Mode
2.3.3.1 System Configuration Register
Operating Modes and On-Chip Memory
RBOOT
DD
0
0
1
0
supply.
Control Bits in HPRIO
(Latched at Reset)
DD
through a pullup resistor
SMOD
0
0
1
1
Memory Map
MDA
Data Sheet
0
1
0
1
for
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