MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 57

IC MCU 3MHZ 512 EEPROM 52-PLCC

MC68HC11E1CFN3

Manufacturer Part Number
MC68HC11E1CFN3
Description
IC MCU 3MHZ 512 EEPROM 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
22
Number Of Timers
16 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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2.5 EEPROM
2.5.1 EEPROM and CONFIG Programming and Erasure
2.5.1.1 Block Protect Register
M68HC11E Family — Rev. 5
MOTOROLA
Some E-series devices contain 512 bytes of on-chip EEPROM. The
MC68HC811E2 contains 2048 bytes of EEPROM with selectable base address. All
E-series devices contain the EEPROM-based CONFIG register.
The erased state of an EEPROM bit is 1. During a read operation, bit lines are
precharged to 1. The floating gate devices of programmed bits conduct and pull the
bit lines to 0. Unprogrammed bits remain at the precharged level and are read as
ones. Programming a bit to 1 causes no change. Programming a bit to 0 changes
the bit so that subsequent reads return 0.
When appropriate bits in the BPROT register are cleared, the PPROG register
controls programming and erasing the EEPROM. The PPROG register can be read
or written at any time, but logic enforces defined programming and erasing
sequences to prevent unintentional changes to EEPROM data. When the EELAT
bit in the PPROG register is cleared, the EEPROM can be read as if it were a ROM.
The on-chip charge pump that generates the EEPROM programming voltage from
V
charge pump and its drive capability are affected by the level of V
frequency of the driving clock. The load depends on the number of bits being
programmed or erased and capacitances in the EEPROM array.
The clock source driving the charge pump is software selectable. When the clock
select (CSEL) bit in the OPTION register is 0, the E clock is used; when CSEL is 1,
an on-chip resistor-capacitor (RC) oscillator is used.
The EEPROM programming voltage power supply voltage to the EEPROM array
is not enabled until there has been a write to PPROG with EELAT set and PGM
cleared. This must be followed by a write to a valid EEPROM location or to the
CONFIG address, and then a write to PPROG with both the EELAT and EPGM bits
set. Any attempt to set both EELAT and EPGM during the same write operation
results in neither bit being set.
This register prevents inadvertent writes to both the CONFIG register and
EEPROM. The active bits in this register are initialized to 1 out of reset and can be
cleared only during the first 64 E-clock cycles after reset in the normal modes.
When these bits are cleared, the associated EEPROM section and the CONFIG
register can be programmed or erased. EEPROM is only visible if the EEON bit in
the CONFIG register is set. The bits in the BPROT register can be written to 1 at
any time to protect EEPROM and the CONFIG register. In test or bootstrap modes,
write protection is inhibited and BPROT can be written repeatedly. Address ranges
for protected areas of EEPROM differ significantly for the MC68HC811E2. Refer to
Figure
DD
uses MOS capacitors, which are relatively small in value. The efficiency of this
Freescale Semiconductor, Inc.
2-16.
For More Information On This Product,
Operating Modes and On-Chip Memory
Go to: www.freescale.com
Operating Modes and On-Chip Memory
DD
and the
Data Sheet
EEPROM
57

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