MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 65

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

3.2.2 Analog Converter
3.2.3 Digital Control
3.2.4 Result Registers
3.2.5 A/D Converter Clocks
M68HC11E Family — Rev. 5
MOTOROLA
Conversion of an analog input selected by the multiplexer occurs in this block. It
contains a digital-to-analog capacitor (DAC) array, a comparator, and a successive
approximation register (SAR). Each conversion is a sequence of eight comparison
operations, beginning with the most significant bit (MSB). Each comparison
determines the value of a bit in the successive approximation register.
The DAC array performs two functions. It acts as a sample and hold circuit during
the entire conversion sequence and provides comparison voltage to the
comparator during each successive comparison.
The result of each successive comparison is stored in the SAR. When a conversion
sequence is complete, the contents of the SAR are transferred to the appropriate
result register.
A charge pump provides switching voltage to the gates of analog switches in the
multiplexer. Charge pump output must stabilize between 7 and 8 volts within up to
100 µs before the converter can be used. The charge pump is enabled by the
ADPU bit in the OPTION register.
All A/D converter operations are controlled by bits in register ADCTL. In addition to
selecting the analog input to be converted, ADCTL bits indicate conversion status
and control whether single or continuous conversions are performed. Finally, the
ADCTL bits determine whether conversions are performed on single or multiple
channels.
Four 8-bit registers ADR[4:1] store conversion results. Each of these registers can
be accessed by the processor in the CPU. The conversion complete flag (CCF)
indicates when valid data is present in the result registers. The result registers are
written during a portion of the system clock cycle when reads do not occur, so there
is no conflict.
The CSEL bit in the OPTION register selects whether the A/D converter uses the
system E clock or an internal RC oscillator for synchronization. When E-clock
frequency is below 750 kHz, charge leakage in the capacitor array can cause
errors, and the internal oscillator should be used. When the RC clock is used,
additional errors can occur because the comparator is sensitive to the additional
system clock noise.
Freescale Semiconductor, Inc.
For More Information On This Product,
Analog-to-Digital (A/D) Converter
Go to: www.freescale.com
Analog-to-Digital (A/D) Converter
Data Sheet
Overview
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