MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 93

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5.2.6 Configuration Control Register
5.3 Effects of Reset
M68HC11E Family — Rev. 5
MOTOROLA
EE[3:0] — EEPROM Mapping Bits
NOSEC — Security Mode Disable Bit
NOCOP — COP System Disable Bit
ROMON — ROM (EPROM) Enable Bit
EEON — EEPROM Enable Bit
When a reset condition is recognized, the internal registers and control bits are
forced to an initial state. Depending on the cause of the reset and the operating
mode, the reset vector can be fetched from any of six possible locations. Refer to
Table
These initial states then control on-chip peripheral systems to force them to known
startup states, as described in the following subsections.
EE[3:0] apply only to MC68HC811E2. Refer to
and On-Chip
Refer to
Refer to
Refer to
Address:
Reset:
Read:
Write:
0 = COP enabled (forces reset on timeout)
1 = COP disabled (does not force reset on timeout)
5-2.
Freescale Semiconductor, Inc.
COP Watchdog Timeout
For More Information On This Product,
Table 5-2. Reset Cause, Reset Vector, and Operating Mode
Clock monitor failure
POR or RESET pin
Section 2. Operating Modes and On-Chip
Section 2. Operating Modes and On-Chip
Section 2. Operating Modes and On-Chip
Cause of Reset
$103F
Bit 7
EE3
Figure 5-3. Configuration Control Register (CONFIG)
0
Memory.
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Resets and Interrupts
EE2
6
0
EE1
5
0
Normal Mode
$FFFE, FFFF
$FFFC, FFFD
$FFFA, FFFB
Vector
EE0
4
0
NOSEC
3
1
Section 2. Operating Modes
NOCOP
Memory.
Memory.
Memory.
$BFFE, $BFFF
$BFFC, $BFFD
$BFFA, $BFFB
or Bootstrap
Special Test
2
1
Resets and Interrupts
ROMON
Effects of Reset
1
1
Data Sheet
EEON
Bit 0
1
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