MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 97

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5.4.1 Highest Priority Interrupt and Miscellaneous Register
M68HC11E Family — Rev. 5
MOTOROLA
RBOOT — Read Bootstrap ROM Bit
SMOD — Special Mode Select Bit
MDA — Mode Select A Bit
IRVNE — Internal Read Visibility/Not E Bit
PSEL[3:0] — Priority Select Bits
Reset:
1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the
Special test:
Single chip:
Expanded:
Has meaning only when the SMOD bit is a 1 (bootstrap mode or special test
mode). At all other times this bit is clear and cannot be written. Refer to
2. Operating Modes and On-Chip Memory
This bit reflects the inverse of the MODB input pin at the rising edge of reset.
Refer to
information.
The mode select A bit reflects the status of the MODA input pin at the rising
edge of reset. Refer to
more information.
The IRVNE control bit allows internal read accesses to be available on the
external data bus during operation in expanded modes. In single-chip and
bootstrap modes, IRVNE determines whether the E clock is driven out an
external pin. For the MC68HC811E2, this bit is IRV and only controls internal
read visibility. Refer to
more information.
These bits select one interrupt source to be elevated above all other I-bit-related
sources and can be written only while the I bit in the CCR is set (interrupts
disabled).
Bootstrap:
RESET pin rising edge. Refer to
Address:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Section 2. Operating Modes and On-Chip Memory
RBOOT
$103C
Bit 7
0
0
1
0
(1)
Go to: www.freescale.com
Figure 5-4. Highest Priority I-Bit Interrupt
Resets and Interrupts
SMOD
and Miscellaneous Register (HPRIO)
6
0
0
1
1
Section 2. Operating Modes and On-Chip Memory
Section 2. Operating Modes and On-Chip Memory
(1)
MDA
Table 2-1. Hardware Mode Select
5
0
1
0
1
(1)
IRVNE
4
0
0
0
1
for more information.
PSEL2
3
0
0
0
0
Reset and Interrupt Priority
PSEL2
2
1
1
1
1
Summary.
Resets and Interrupts
for more
PSEL1
1
1
1
1
1
Data Sheet
Section
PSEL0
Bit 0
0
0
0
0
for
for
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