MC68HC11E1CFN2R2 Freescale Semiconductor, MC68HC11E1CFN2R2 Datasheet - Page 113

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MC68HC11E1CFN2R2

Manufacturer Part Number
MC68HC11E1CFN2R2
Description
IC MCU 512 EEPROM 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN2R2

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Other names
MC68HC11E1CFN2TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFN2R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
6.6 Port E
6.7 Handshake Protocol
M68HC11E Family — Rev. 5
MOTOROLA
Alternate Function:
Bits [7:6] — Unimplemented
DDRD[5:0] — Port D Data Direction Bits
Port E is used for general-purpose static inputs or pins that share functions with the
analog-to-digital (A/D) converter system. When some port E pins are being used
for general-purpose input and others are being used as A/D inputs, PORTE should
not be read during the sample portion of an A/D conversion.
Simple and full handshake input and output functions are available on ports B and
C pins in single-chip mode. In simple strobed mode, port B is a strobed output port
and port C is a latching input port. The two activities are available simultaneously.
The STRB output is pulsed for two E-clock periods each time there is a write to the
PORTB register. The INVB bit in the PIOC register controls the polarity of STRB
pulses. Port C levels are latched into the alternate port C latch (PORTCL) register
on each assertion of the STRA input. STRA edge select, flag, and interrupt enable
bits are located in the PIOC register. Any or all of the port C lines can still be used
as general-purpose I/O while in strobed input mode.
Always read 0
When DDRD bit 5 is 1 and MSTR = 1 in SPCR, PD5/SS is a general-purpose
output and mode fault logic is disabled.
Address:
Address:
Reset:
Read:
Write:
Reset:
Read:
Write:
0 = Input
1 = Output
Freescale Semiconductor, Inc.
For More Information On This Product,
$1009
Bit 7
$100A
Bit 7
PE7
AN7
0
Figure 6-8. Port D Data Direction Register (DDRD)
Figure 6-9. Port E Data Register (PORTE)
Parallel Input/Output (I/O) Ports
Go to: www.freescale.com
= Unimplemented
PE6
AN6
6
0
6
DDRD5
PE5
AN5
5
0
5
Indeterminate after reset
DDRD4
PE4
AN4
4
0
4
DDRD3
PE3
AN3
3
0
3
Parallel Input/Output (I/O) Ports
DDRD2
PE2
AN2
2
0
2
DDRD1
PE1
AN1
1
0
1
Data Sheet
DDRD0
Bit 0
Bit 0
PE0
AN0
Port E
0
113

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