MC68HC11E1CFN2R2 Freescale Semiconductor, MC68HC11E1CFN2R2 Datasheet - Page 136

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MC68HC11E1CFN2R2

Manufacturer Part Number
MC68HC11E1CFN2R2
Description
IC MCU 512 EEPROM 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN2R2

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Other names
MC68HC11E1CFN2TR

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFN2R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Serial Peripheral Interface (SPI)
8.5.1 Master In/Slave Out
8.5.2 Master Out/Slave In
8.5.3 Serial Clock
8.5.4 Slave Select
Data Sheet
136
Any SPI output line must have its corresponding data direction bit in DDRD register
set. If the DDR bit is clear, that line is disconnected from the SPI logic and becomes
a general-purpose input. All SPI input lines are forced to act as inputs regardless
of the state of the corresponding DDR bits in DDRD register.
MISO is one of two unidirectional serial data signals. It is an input to a master
device and an output from a slave device. The MISO line of a slave device is placed
in the high-impedance state if the slave device is not selected.
The MOSI line is the second of the two unidirectional serial data signals. It is an
output from a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge that the slave
device uses to latch the data.
SCK, an input to a slave device, is generated by the master device and
synchronizes data movement in and out of the device through the MOSI and MISO
lines. Master and slave devices are capable of exchanging a byte of information
during a sequence of eight clock cycles.
Four possible timing relationships can be chosen by using control bits CPOL and
CPHA in the serial peripheral control register (SPCR). Both master and slave
devices must operate with the same timing. The SPI clock rate select bits,
SPR[1:0], in the SPCR of the master device, select the clock rate. In a slave device,
SPR[1:0] have no effect on the operation of the SPI.
The slave select (SS) input of a slave device must be externally asserted before a
master device can exchange data with the slave device. SS must be low before
data transactions and must stay low for the duration of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault error flag
(MODF) is set in the serial peripheral status register (SPSR). To disable the mode
fault circuit, write a 1 in bit 5 of the port D data direction register. This sets the SS
pin to act as a general-purpose output rather than the dedicated input to the slave
select circuit, thus inhibiting the mode fault flag. The other three lines are dedicated
to the SPI whenever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS. CPHA
settings should be identical for master and slave. When CPHA = 0, the shift clock
is the OR of SS with SCK. In this clock phase mode, SS must go high between
successive characters in an SPI message. When CPHA = 1, SS can be left low
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
M68HC11E Family — Rev. 5
MOTOROLA

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