MC68HC11E1CFN2R2 Freescale Semiconductor, MC68HC11E1CFN2R2 Datasheet - Page 149

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MC68HC11E1CFN2R2

Manufacturer Part Number
MC68HC11E1CFN2R2
Description
IC MCU 512 EEPROM 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN2R2

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Other names
MC68HC11E1CFN2TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFN2R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
9.4.1 Timer Output Compare Registers
M68HC11E Family — Rev. 5
MOTOROLA
register is compared to the free-running counter value during each E-clock cycle.
If a match is found, the particular output compare flag is set in timer interrupt flag
register 1 (TFLG1). If that particular interrupt is enabled in the timer interrupt mask
register 1 (TMSK1), an interrupt is generated. In addition to an interrupt, a specified
action can be initiated at one or more timer output pins. For OC[5:2], the pin action
is controlled by pairs of bits (OMx and OLx) in the TCTL1 register. The output
action is taken on each successful compare, regardless of whether or not the OCxF
flag in the TFLG1 register was previously cleared.
OC1 is different from the other output compares in that a successful OC1 compare
can affect any or all five of the OC pins. The OC1 output action taken when a match
is found is controlled by two 8-bit registers with three bits unimplemented: the
output compare 1 mask register, OC1M, and the output compare 1 data register,
OC1D. OC1M specifies which port A outputs are to be used, and OC1D specifies
what data is placed on these port pins.
All output compare registers are 16-bit read-write. Each is initialized to $FFFF at
reset. If an output compare register is not used for an output compare function, it
can be used as a storage location. A write to the high-order byte of an output
compare register pair inhibits the output compare function for one bus cycle. This
inhibition prevents inappropriate subsequent comparisons. Coherency requires a
complete 16-bit read or write. However, if coherency is not needed, byte accesses
can be used.
For output compare functions, write a comparison value to output compare
registers TOC1–TOC4 and TI4/O5. When TCNT value matches the comparison
value, specified pin actions occur.
Register name: Timer Output Compare 1 Register (High)
Register name: Timer Output Compare 1 Register (Low)
Reset:
Reset:
Read:
Read:
Write:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 9-8. Timer Output Compare 1 Register Pair (TOC1)
Bit 15
Bit 7
Bit 7
Bit 7
1
1
Go to: www.freescale.com
Bit 14
Bit 6
6
1
6
1
Timing System
Bit 13
Bit 5
5
1
5
1
Bit 12
Bit 4
4
1
4
1
Address: $1017
Address: $1016
Bit 11
Bit 3
3
1
3
1
Bit 10
Bit 2
2
1
2
1
Bit 9
Bit 1
Output Compare
1
1
1
1
Timing System
Data Sheet
Bit 0
Bit 0
Bit 0
Bit 8
1
1
149

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