MC68HC11E1CFN2R2 Freescale Semiconductor, MC68HC11E1CFN2R2 Datasheet - Page 28

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MC68HC11E1CFN2R2

Manufacturer Part Number
MC68HC11E1CFN2R2
Description
IC MCU 512 EEPROM 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN2R2

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Other names
MC68HC11E1CFN2TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFN2R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
General Description
1.4.10 Port Signals
1.4.10.1 Port A
Data Sheet
28
Port pins have different functions in different operating modes. Pin functions for
port A, port D, and port E are independent of operating modes. Port B and port C,
however, are affected by operating mode. Port B provides eight general-purpose
output signals in single-chip operating modes. When the microcontroller is in
expanded multiplexed operating mode, port B pins are the eight high-order address
lines.
Port C provides eight general-purpose input/output signals when the MCU is in the
single-chip operating mode. When the microcontroller is in the expanded
multiplexed operating mode, port C pins are a multiplexed address/data bus.
Refer to
operating modes. Terminate unused inputs and input/output (I/O) pins configured
as inputs high or low.
In all operating modes, port A can be configured for three timer input capture (IC)
functions and four timer output compare (OC) functions. An additional pin can be
configured as either the fourth IC or the fifth OC. Any port A pin that is not currently
being used for a timer function can be used as either a general-purpose input or
output line. Only port A pins PA7 and PA3 have an associated data direction
control bit that allows the pin to be selectively configured as input or output. Bits
DDRA7 and DDRA3 located in PACTL register control data direction for PA7 and
PA3, respectively. All other port A pins are fixed as either input or output.
PA7 can function as general-purpose I/O or as timer output compare for OC1. PA7
is also the input to the pulse accumulator, even while functioning as a
general-purpose I/O or an OC1 output.
PA6–PA4 serve as either general-purpose outputs, timer input captures, or timer
output compare 2–4. In addition, PA6–PA4 can be controlled by OC1.
PA3 can be a general-purpose I/O pin or a timer IC/OC pin. Timer functions
associated with this pin include OC1 and IC4/OC5. IC4/OC5 is software selectable
as either a fourth input capture or a fifth output compare. PA3 can also be
configured to allow OC1 edges to trigger IC4 captures.
PA2–PA0 serve as general-purpose inputs or as IC1–IC3.
PORTA can be read at any time. Reads of pins configured as inputs return the logic
level present on the pin. Pins configured as outputs return the logic level present
at the pin driver input. If written, PORTA stores the data in an internal latch, bits 7
and 3. It drives the pins only if they are configured as outputs. Writes to PORTA do
not change the pin state when pins are configured for timer input captures or output
compares. Refer to
Freescale Semiconductor, Inc.
Table 1-1
For More Information On This Product,
Go to: www.freescale.com
for a functional description of the 40 port signals within different
Section 6. Parallel Input/Output (I/O)
General Description
M68HC11E Family — Rev. 5
Ports.
MOTOROLA

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