MC68HC11E1CFN2R2 Freescale Semiconductor, MC68HC11E1CFN2R2 Datasheet - Page 35

• Manufacturer Part Number: MC68HC11E1CFN2R2
• Description: IC MCU 512 EEPROM 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN2R2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Other names: MC68HC11E1CFN2TR

2.2.4 Bootstrap Mode
2.3 Memory Map
M68HC11E Family — Rev. 5
MOTOROLA
configuration (CONFIG) register, programming calibration data into electrically
erasable, programmable read-only memory (EEPROM), and supporting emulation
and debugging during development.
When the MCU is reset in special bootstrap mode, a small on-chip read-only
memory (ROM) is enabled at address $BF00–$BFFF. The ROM contains a
bootloader program and a special set of interrupt and reset vectors. The MCU
fetches the reset vector, then executes the bootloader.
Bootstrap mode is a special variation of the single-chip mode. Bootstrap mode
allows special-purpose programs to be entered into internal random-access
memory (RAM). When bootstrap mode is selected at reset, a small bootstrap ROM
becomes present in the memory map. Reset and interrupt vectors are located in
this ROM at $BFC0–$BFFF. The bootstrap ROM contains a small program which
initializes the serial communications interface (SCI) and allows the user to
download a program into on-chip RAM. The size of the downloaded program can
be as large as the size of the on-chip RAM. After a 4-character delay, or after
receiving the character for the highest address in RAM, control passes to the
loaded program at $0000. Refer to
and
Use of an external pullup resistor is required when using the SCI transmitter pin
because port D pins are configured for wired-OR operation by the bootloader. In
bootstrap mode, the interrupt vectors are directed to RAM. This allows the use of
interrupts through a jump table. Refer to the application note AN1060 entitled
M68HC11 Bootstrap
The operating mode determines memory mapping and whether external
addresses can be accessed. Refer to
Figure
families comprising the M68HC11 E series of MCUs.
Memory locations for on-chip resources are the same for both expanded and
single-chip modes. Control bits in the configuration (CONFIG) register allow
EPROM and EEPROM (if present) to be disabled from the memory map. The RAM
is mapped to $0000 after reset. It can be placed at any 4-Kbyte boundary ($x000)
by writing an appropriate value to the RAM and I/O map register (INIT). The 64-byte
register block is mapped to $1000 after reset and also can be placed at any 4-Kbyte
boundary ($x000) by writing an appropriate value to the INIT register. If RAM and
registers are mapped to the same boundary, the first 64 bytes of RAM will be
inaccessible.
Refer to
Reset states shown are for single-chip mode only.
Figure
Freescale Semiconductor, Inc.
2-5, and
Figure
For More Information On This Product,
2-6.
Operating Modes and On-Chip Memory
Figure
2-7, which details the MCU register and control bit assignments.
Go to: www.freescale.com
Mode, that is included in this data book.
2-6, which illustrate the memory maps for each of the three
Figure
Figure
2-2,
Operating Modes and On-Chip Memory
2-2,
Figure
Figure
2-3,
2-3,
Figure
Figure
2-4,
Memory Map
2-4,
Figure
Data Sheet
2-5,
35