MC68HC11E1CFN2R2 Freescale Semiconductor, MC68HC11E1CFN2R2 Datasheet - Page 95

• Manufacturer Part Number: MC68HC11E1CFN2R2
• Description: IC MCU 512 EEPROM 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN2R2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Other names: MC68HC11E1CFN2TR

5.3.6 Computer Operating Properly (COP)
5.3.7 Serial Communications Interface (SCI)
5.3.8 Serial Peripheral Interface (SPI)
5.3.9 Analog-to-Digital (A/D) Converter
5.3.10 System
M68HC11E Family — Rev. 5
MOTOROLA
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG
register is cleared and disabled if NOCOP is set. The COP rate is set for the
shortest duration timeout.
The reset condition of the SCI system is independent of the operating mode. At
reset, the SCI baud rate control register (BAUD) is initialized to $04. All transmit
and receive interrupts are masked and both the transmitter and receiver are
disabled so the port pins default to being general-purpose I/O lines. The SCI frame
format is initialized to an 8-bit character size. The send break and receiver wakeup
functions are disabled. The TDRE and TC status bits in the SCI status register
(SCSR) are both 1s, indicating that there is no transmit data in either the transmit
data register or the transmit serial shift register. The RDRF, IDLE, OR, NF, FE, PF,
and RAF receive-related status bits in the SCI control register 2 (SCCR2) are
cleared.
The SPI system is disabled by reset. The port pins associated with this function
default to being general-purpose I/O lines.
The analog-to-digital (A/D) converter configuration is indeterminate after reset. The
ADPU bit is cleared by reset, which disables the A/D system. The conversion
complete flag is indeterminate.
The EEPROM programming controls are disabled, so the memory system is
configured for normal read operation. PSEL[3:0] are initialized with the value
%0110, causing the external IRQ pin to have the highest I-bit interrupt priority. The
IRQ pin is configured for level-sensitive operation (for wired-OR systems). The
RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status of the
MODB and MODA inputs at the rising edge of reset. MODA and MODB inputs
select one of the four operating modes. After reset, writing SMOD and MDA in
special modes causes the MCU to change operating modes. Refer to the
description of HPRIO register in
Memory
to specify that an oscillator startup delay is imposed upon recovery from stop
mode. The clock monitor system is disabled because CME is cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
for a detailed description of SMOD and MDA. The DLY control bit is set
Go to: www.freescale.com
Resets and Interrupts
Section 2. Operating Modes and On-Chip
Resets and Interrupts
Effects of Reset
Data Sheet
95