MC68HC11E1CFN2R2 Freescale Semiconductor, MC68HC11E1CFN2R2 Datasheet - Page 96

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MC68HC11E1CFN2R2

Manufacturer Part Number
MC68HC11E1CFN2R2
Description
IC MCU 512 EEPROM 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN2R2

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Other names
MC68HC11E1CFN2TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFN2R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Resets and Interrupts
5.4 Reset and Interrupt Priority
Data Sheet
96
Resets and interrupts have a hardware priority that determines which reset or
interrupt is serviced first when simultaneous requests occur. Any maskable
interrupt can be given priority over other maskable interrupts.
The first six interrupt sources are not maskable. The priority arrangement for these
sources is:
The maskable interrupt sources have this priority arrangement:
Any one of these interrupts can be assigned the highest maskable interrupt priority
by writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise,
the priority arrangement remains the same. An interrupt that is assigned highest
priority is still subject to global masking by the I bit in the CCR, or by any associated
local bits. Interrupt vectors are not affected by priority assignment. To avoid race
conditions, HPRIO can be written only while I-bit interrupts are inhibited.
10. Timer input capture 4/output compare 5
11. Timer overflow
12. Pulse accumulator overflow
13. Pulse accumulator input edge
14. SPI transfer complete
15. SCI system (refer to
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ interrupt
5. Illegal opcode interrupt
6. Software interrupt (SWI)
1. IRQ
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Resets and Interrupts
Figure
5-7)
M68HC11E Family — Rev. 5
MOTOROLA

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