MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet
MC68HC908AS60CFN
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MC68HC908AS60/D REV 1 MC68HC908AS60 Technical Data HCMOS Microcontroller Unit ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 33 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Section 3. Random-Access Memory (RAM Section 4. FLASH-1 Memory . . . . . . . . . . . . . . . . . . . . . . 63 Section 5. FLASH-2 Memory . . . . . . . . . . . . . . . . . . . . . . 77 Section 6. EEPROM Section 7. EEPROM 101 Section 8. Central Processor Unit (CPU 113 Section 9. System Integration Module (SIM 133 Section 10. Clock Generator Module (CGM 155 Section 11 ...
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... Freescale Semiconductor, Inc. List of Sections Section 18. Serial Peripheral Interface (SPI 259 Section 19. Modulo Timer (TIM 291 Section 20. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 301 Section 21. Byte Data Link Section 22. Timer Interface Module A (TIMA- 375 Section 23. Analog-to-Digital Converter (ADC-15 407 Section 24. Electrical Specifications 419 Section 25. Mechanical Specifications . . . . . . . . . . . . . 433 Section 26 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 1.5.13 1.5.14 1.5.15 1.5.16 1.5.17 MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Section 1. General Description Contents ...
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... Freescale Semiconductor, Inc. Table of Contents 2.1 2.2 2.3 3.1 3.2 3.3 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.8.1 4.8.2 4.9 4.9.1 4.9.2 5.1 5.2 5.3 Technical Data Section 2. Memory Map Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Section 3. Random-Access Memory (RAM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Introduction ...
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... Freescale Semiconductor, Inc. 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.10.1 5.10.2 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.5 6.5.1 6.5.2 MC68HC908AS60 — Rev. 1.0 For More Information On This Product, FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . 81 FLASH Erase Operation ...
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... Freescale Semiconductor, Inc. Table of Contents 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.5 7.5.1 7.5.2 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.6.1 8.6.2 Technical Data Section 7. EEPROM-2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Features ...
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... Freescale Semiconductor, Inc. 8.7 8.8 8.9 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.4 9.4.1 9.4.2 9.4.2.1 9.4.2.2 9.4.2.3 9.4.2.4 9.4.2.5 9.5 9.5.1 9.5.2 9.5.3 9.6 9.6.1 9.6.1.1 9.6.1.2 9.6.2 9.6.3 9.6.4 9.7 9.7.1 9.7.2 MC68HC908AS60 — Rev. 1.0 For More Information On This Product, CPU During Break Interrupts ...
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... Freescale Semiconductor, Inc. Table of Contents 9.8 9.8.1 9.8.2 9.8.3 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.2.1 10.4.2.2 10.4.2.3 10.4.2.4 10.4.2.5 10.4.3 10.4.4 10.5 10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 10.5.6 10.5.7 10.5.8 10.6 10.6.1 10.6.2 10.6.3 10.7 Technical Data SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 SIM Break Status Register ...
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... Freescale Semiconductor, Inc. 10.8 10.8.1 10.8.2 10.9 10.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 176 10.10.1 Acquisition/Lock Time Definitions 176 10.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .177 10.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 178 11.1 11.2 11.3 12.1 12.2 12.3 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.5 12.5.1 12 ...
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... Freescale Semiconductor, Inc. Table of Contents 13.1 13.2 13.3 13.4 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 13.4.6 13.4.7 14.1 14.2 14.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.4.6 14.4.7 14.4.8 14.5 14.6 14.7 Technical Data Section 13. Monitor ROM (MON) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Features ...
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... Freescale Semiconductor, Inc. 14.8 14.8.1 14.8.2 14.9 15.1 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.5 15.6 15.7 15.7.1 15.7.2 16.1 16.2 16.3 16.4 16.5 16.6 16.7 MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Stop Mode ...
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... Freescale Semiconductor, Inc. Table of Contents 17.1 17.2 17.3 17.4 17.5 17.5.1 17.5.2 17.5.2.1 17.5.2.2 17.5.2.3 17.5.2.4 17.5.2.5 17.5.2.6 17.5.3 17.5.3.1 17.5.3.2 17.5.3.3 17.5.3.4 17.5.3.5 17.5.3.6 17.5.3.7 17.5.3.8 17.6 17.6.1 17.6.2 17.7 17.8 17.8.1 17.8.2 17.9 17.9.1 17.9.2 17.9.3 17.9.4 Technical Data Section 17 ...
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... Freescale Semiconductor, Inc. 17.9.5 17.9.6 17.9.7 18.1 18.2 18.3 18.4 18.5 18.5.1 18.5.2 18.6 18.6.1 18.6.2 18.6.3 18.6.4 18.7 18.7.1 18.7.2 18.8 18.9 18.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 18.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 18.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 18.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18 ...
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... Freescale Semiconductor, Inc. Table of Contents 18.13.4 SS (Slave Select 281 18.13.5 V 18.14 I/O Registers 282 18.14.1 SPI Control Register 283 18.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . 285 18.14.3 SPI Data Register 288 19.1 19.2 19.3 19.4 19.5 19.6 19.6.1 19.6.2 19.7 19.8 19 ...
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... Freescale Semiconductor, Inc. 20.5 20.5.1 20.5.2 20.6 20.6.1 20.6.2 20.7 20.7.1 20.7.2 20.8 20.8.1 20.8.2 20.9 20.9.1 20.9.2 20.10 Port 323 20.10.1 Port H Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 20.10.2 Data Direction Register 324 Section 21. Byte Data Link Controller-Digital (BDLC-D) 21.1 21.2 21.3 21.4 21 ...
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... Freescale Semiconductor, Inc. Table of Contents 21.5 21.5.1 21.5.1.1 21.5.1.2 21.5.2 21.5.2.1 21.5.2.2 21.5.2.3 21.5.2.4 21.5.2.5 21.5.2.6 21.5.2.7 21.5.2.8 21.5.2.9 21.5.3 21.5.3.1 21.5.3.2 21.5.3.3 21.5.3.4 21.5.3.5 21.5.3.6 21.5.3.7 21.5.3.8 21.5.3.9 21.5.4 21.5.4.1 21.5.4.2 21.5.4.3 21.5.4.4 21.5.4.5 21.5.4.6 21.5.4.7 21.5.4.8 21.5.4.9 21.5.4.10 21.5.4.11 21 ...
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... Freescale Semiconductor, Inc. 21.6.4 21.6.5 21.6.5.1 21.6.5.2 21.6.5.3 21.6.5.4 21.6.5.5 21.7 21.7.1 21.7.2 21.7.3 21.7.4 21.7.5 21.8 21.8.1 21.8.2 22.1 22.2 22.3 22.4 22.4.1 22.4.2 22.4.3 22.4.3.1 22.4.3.2 22.4.4 22.4.4.1 22.4.4.2 22.4.4.3 22.5 22.6 22.6.1 22.6.2 MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Digital Loopback Multiplexer ...
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... Freescale Semiconductor, Inc. Table of Contents 22.7 22.8 22.8.1 22.8.2 22.9 22.9.1 22.9.2 22.9.3 22.9.4 22.9.5 23.1 23.2 23.3 23.4 23.4.1 23.4.2 23.4.3 23.4.4 23.4.5 23.5 23.6 23.6.1 23.6.2 23.7 23.7.1 23.7.2 23.7.3 Technical Data TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 391 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 TIMA Clock Pin (PTD6/ATD14/TCLK 392 TIMA Channel I/O Pins (PTF3– ...
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... Freescale Semiconductor, Inc. 23.8 23.8.1 23.8.2 23.8.3 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 24.10 CGM Component Information 428 24.11 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . 429 24.12 Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 429 24.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 24.14 BDLC Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . . 431 24 ...
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... Freescale Semiconductor, Inc. Table of Contents 26.1 26.2 26.3 Technical Data Section 26. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437 Index Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Figure 1-1 1-2 1-3 1-4 2-1 2-2 4-1 4-2 4-3 4-4 5-1 5-2 6-1 6-2 6-3 7-1 7-2 7-3 8-1 8-2 8-3 8-4 8-5 MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Title MCU Block Diagram for the MC68HC08ASxx Emulator ...
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... Freescale Semiconductor, Inc. List of Figures Figure 8-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 9-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 147 9-12 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9-13 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 149 9-14 Wait Recovery from Internal Reset 149 9-15 Stop Mode Entry Timing ...
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... Freescale Semiconductor, Inc. Figure 13-1 Monitor Mode Circuit 193 13-2 Monitor Data Format 195 13-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 13-5 Break Transaction 196 13-6 Monitor Mode Entry Timing 200 14-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 14-2 COP Control Register (COPCTL 207 15-1 LVI Module Block Diagram ...
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... Freescale Semiconductor, Inc. List of Figures Figure 18-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 18-2 SPI Module Block Diagram 263 18-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 264 18-4 Transmission Format (CPHA = 267 18-5 Transmission Format (CPHA = 268 18-6 Transmission Start Delay (Master 270 18-7 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 271 18-8 Clearing SPRF When OVRF Interrupt Is Not Enabled ...
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... Freescale Semiconductor, Inc. Figure 20-16 Port E I/O Circuit 317 20-17 Port F Data Register (PTF 318 20-18 Data Direction Register F (DDRF 319 20-19 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 20-20 Port G Data Register (PTG 320 20-21 Data Direction Register G (DDRG 321 20-22 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 20-23 Port H Data Register (PTH) ...
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... Freescale Semiconductor, Inc. List of Figures Figure 22-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 385 22-4 Timer A Status and Control Register (TASC 393 22-5 TIMA Counter Registers (TCNTH and TCNTL 395 22-6 TIMA Counter Modulo Registers 22-7 TIMA Channel Status 22-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 22-9 TIMA Channel Registers (TACH0H/L– ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Table 1-1 1-2 2-1 4-1 4-2 5-1 5-2 6-1 6-2 6-3 7-1 7-2 7-3 8-1 8-2 9-1 9-2 10-1 Variable Definitions .163 10-2 VCO Frequency Multiplier (N) Selection 173 11-1 COP Time Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 MC68HC908AS60 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. List of Tables Table 13-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 13-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13-3 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 197 13-4 WRITE (Write Memory) Command 197 13-5 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 198 13-6 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 198 13-7 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 198 13-8 RUN (Run User Program) Command ...
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... Freescale Semiconductor, Inc. Table 20-8 Port H Pin Functions 325 21-1 BDLC J1850 Bus Error Summary 356 21-2 BDLC Transceiver Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21-3 BDLC Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21-4 BDLC Transmit In-Frame Response 21-5 BDLC Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 22-1 Prescaler Selection .394 22-2 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 401 23-1 Mux Channel Select ...
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... Freescale Semiconductor, Inc. List of Tables Technical Data List of Tables For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 1.1 Contents 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 1.5.13 1.5.14 1.5.15 1.5.16 1.5.17 MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Section 1. General Description Introduction ...
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... Freescale Semiconductor, Inc. General Description 1.2 Introduction The MC68HC908AS60 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCU). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types ...
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... Freescale Semiconductor, Inc. • • • • • • • • Features of the CPU08 include: • • • • • • • • • • 1.4 MCU Block Diagram Figure 1-1 MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Serial communications interface module (SCI) ...
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... Freescale Semiconductor, Inc. General Description PTA PTB PTC DDRC DDRA DDRB Technical Data PTD PTE DDRD DDRE General Description For More Information On This Product, Go to: www.freescale.com PTF PTG PTH DDRF DDRG DDRH BDTxD BDRxD MC68HC908AS60 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. 1.5 Pin Assignments Figure 1-2 plastic leaded chip carrier (PLCC) package. PTC4 8 IRQ 9 RST 10 PTF0/TACH2 11 PTF1/TACH3 12 PTF2/TACH4 13 PTF3/TACH5 14 BDRxD 15 BDTxD 16 PTE0/TxD 17 PTE1/RxD 18 PTE2/TACH0 19 PTE3/TACH1 20 Figure 1-2. MC68HC908AS60 (52-Pin PLCC) MC68HC908AS60 — Rev. 1.0 For More Information On This Product, ...
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... Freescale Semiconductor, Inc. General Description Figure 1-3 quad flat pack (QFP) package. PTC4 1 IRQ 2 RST 3 PTF0/TACH2 4 PTF1/TACH3 5 PTF2/TACH4 6 PTF3/TACH5 7 PTF4 8 BDRxD 9 BDTxD 10 PTF5 11 PTF6 12 PTE0/TxD 13 PTE1/RxD 14 PTE2/TACH0 15 PTE3/TACH1 16 Figure 1-3. MC68HC908AS60 (64-Pin QFP) NOTE: The following pin descriptions are for quick reference only. For a more ...
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... Freescale Semiconductor, Inc. 1.5.1 Power Supply Pins (V V and V DD from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as shown in Figure possible ...
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... Freescale Semiconductor, Inc. General Description 1.5.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See 1.5.3 External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system ...
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... Freescale Semiconductor, Inc. 1.5.7 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Section 23. Analog-to-Digital Converter 1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0) PTA7–PTA0 are general-purpose bidirectional input/output (I/O) port pins. See 1.5.9 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) Port 8-bit special function port that shares all eight pins with the analog-to-digital converter (ADC) ...
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... Freescale Semiconductor, Inc. General Description Interface 22. Timer Interface Module A (I/O) 1.5.13 Port F I/O Pins (PTF7–PTF0/TACH2) Port 7-bit special function port that shares six of its pins with the timer interface module (TIMA-6). See Module A (TIMA-6) 1.5.14 Port G I/O Pins (PTG2–PTG0) Port 3-bit, general-purpose, bidirectional I/O port. 1.5.15 Port H I/O Pins (PTH1– ...
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... Freescale Semiconductor, Inc. Pin Name PTA7–PTA0 PTB7/ATD7–PTB0/ATD0 PTC5–PTC0 PTC5 available in 64-pin package only PTD7 Available in 64-pin package only PTD6/ATD14/TACLK ADC channel PTD5/ATD13 ADC channel PTD4/ATD12/TBCLK ADC channel TBCLK for 64-pin package only PTD3/ATD11–PTD0/ATD8 ADC channel PTE7/SPSCK PTE6/MOSI ...
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... Freescale Semiconductor, Inc. General Description Table 1-1. External Pins Summary (Continued) Pin Name PTF3/TACH5 PTF2/TACH4 PTF1/TACH3 PTF0/TACH2 PTG2–PTG0 Available in 64-pin package only PTH1–PTH0 Available in 64-pin package only DDA DDAREF ADC reference voltage for 52-pin package only SSA REFL REFL ...
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... Freescale Semiconductor, Inc. MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Table 1-2. Clock Source Summary Module ADC BDLC COP CPU EEPROM SPI SCI TIMA-6 Bus clock or PTD6/ATD14/TACLK TIM SIM CGMOUT and CGMXCLK IRQ BRK LVI CGM General Description Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. General Description Technical Data General Description For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 2.1 Contents 2.2 2.3 2.2 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in • • • • • These definitions apply to the memory map representation of reserved and unimplemented locations. • ...
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... Freescale Semiconductor, Inc. Memory Map Technical Data $0000 I/O REGISTERS 64 BYTES $003F $0040 UNIMPLEMENTED 11 BYTES $004A $004B I/O REGISTERS 5 BYTES $004F $0050 RAM-1 1024 BYTES $044F $0450 FLASH-2 432 BYTES $05FF $0600 EEPROM-2 512 BYTES $07FF $0800 EEPROM-1 512 BYTES $09FF ...
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... Freescale Semiconductor, Inc. $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FE11 $FE12 $FE17 $FE18 $FE19 $FE1A $FE1B $FE1C $FE1D $FE1E $FE1F $FE20 $FEFF $FF00 $FF7F $FF80 $FF81 $FF82 $FFCB $FFCC $FFD9 $FFDA $FFFF MC68HC908AS60 — Rev. 1.0 For More Information On This Product, ...
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... Freescale Semiconductor, Inc. Memory Map 2.3 Input/Output Section Addresses $0000–$003F, shown in control, status, and data registers. Additional input/output (I/O) registers have these addresses: • • • • • • • • • • • • • • • • ...
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... Freescale Semiconductor, Inc. Addr. Register Name Port A Data Register $0000 (PTA) See page 304. Port B Data Register $0001 (PTB) See page 306. Port C Data Register $0002 (PTC) See page 308. Port D Data Register $0003 (PTD) See page 311. Data Direction Register A ...
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... Freescale Semiconductor, Inc. Memory Map Addr. Register Name $000A Port G Data Register (PTG) See page 320. $000B Port H Data Register (PTH) See page 323. $000C Data Direction Register E (DDRE) See page 316. $000D Data Direction Register F (DDRF) See page 319. $000E ...
Page 53
... Freescale Semiconductor, Inc. Addr. Register Name $0014 SCI Control Register 2 (SCC2) See page 246. $0015 SCI Control Register 3 (SCC3) See page 248. $0016 SCI Status Register 1 (SCS1) See page 250. $0017 SCI Status Register 2 (SCS2) See page 253. $0018 SCI Data Register (SCDR) See page 254 ...
Page 54
... Freescale Semiconductor, Inc. Memory Map Addr. Register Name $001F Configuration Write-Once Register (CONFIG-1) See page 182. $0020 Timer A Status and Control Register (TASC) See page 393. $0021 Unimplemented $0022 Timer A Counter Register High (TACNTH) See page 395. $0023 Timer A Counter Register Low (TACNTL) See page 395 ...
Page 55
... Freescale Semiconductor, Inc. Addr. Register Name $002A Timer A Channel 1 Register High (TACH1H) See page 403. $002B Timer A Channel 1 Register Low (TACH1L) See page 403. $002C Timer A Channel 2 Status and Control Register (TASC2) See page 397. $002D Timer A Channel 2 Register High (TACH2H) See page 403 ...
Page 56
... Freescale Semiconductor, Inc. Memory Map Addr. Register Name $0034 Timer A Channel 4 Register Low (TACH4L) See page 403. $0035 Timer A Channel 5 Status and Control Register (TASC5) See page 397. $0036 Timer A Channel 5 Register High (TACH5H) See page 403. $0037 Timer A Channel 5 Register Low (TACH5L) See page 403 ...
Page 57
... Freescale Semiconductor, Inc. Addr. Register Name $003E BDLC State Vector Register (BSVR) See page 370. $003F BDLC Data Register (BDR) See page 372. $0040 Unimplemented $004A $004B TIM Status and Control Register (TSC) See page 296. $004C TIM Counter Register High (TCNTH) See page 298 ...
Page 58
... Freescale Semiconductor, Inc. Memory Map Addr. Register Name $FE03 SIM Break Flag Control Register (SBFCR) See page 154. $FE09 Reserved $FE0B FLASH-1 Control Register (FLCR1) See page 65. $FE0C Break Address Register High (BRKH) See page 190. $FE0D Break Address Register Low (BRKL) See page 190 ...
Page 59
... Freescale Semiconductor, Inc. Addr. Register Name $FE1B EEPROM-2 Array Control Register (EEACR2) See page 110. $FE1C EEPROM-1 Non-volatile Register (EENVR1) See page 98. $FE1D EEPROM-1 Control Register (EECR1) See page 96. $FE1E Reserved $FE1F EEPROM-1 Array Control Register (EEACR1) See page 98. $FF80 FLASH-1 Block Protect Register (FLBPR1) See page 72 ...
Page 60
... Freescale Semiconductor, Inc. Memory Map Technical Data Table 2-1. Vector Addresses Address $FFDA TIM vector (high) $FFDB TIM vector (low) $FFDC BDLC vector (high) $FFDD BDLC vector (low) $FFDE ADC vector (high) $FFDF ADC vector (low) $FFE0 SCI transmit vector (high) ...
Page 61
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 3.3 3.2 Introduction This section describes the 2048 bytes of random-access memory (RAM). 3.3 Functional Description Addresses $0050–$044F and $0A00–$0DFF are the RAM locations. ...
Page 62
... Freescale Semiconductor, Inc. Random-Access Memory (RAM) Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805, M146805, and M68HC05 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address ...
Page 63
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.8.1 4.8.2 4.9 4.9.1 4.9.2 4.2 Introduction This section describes the operation of the embedded FLASH-1 memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AS60 — ...
Page 64
... Freescale Semiconductor, Inc. FLASH-1 Memory 4.3 Functional Description The FLASH memory physically consists of two independent arrays of 32 Kbytes with an additional 38 bytes of user vectors and two bytes of block protection. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program and erase operations are facilitated through control bits in a memory mapped register ...
Page 65
... Freescale Semiconductor, Inc. The row architecture for this array is: • • • • • Programming tools are available from Motorola. Contact a local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents. 4.4 FLASH-1 Control Register The FLASH-1 control register (FLCR1) controls FLASH-1 program, erase, and margin read operations ...
Page 66
... Freescale Semiconductor, Inc. FLASH-1 Memory BLK1— Block Erase Control Bit This read/write bit together with BLK0 allows erasing of blocks of varying size. See available block sizes. BLK0 — Block Erase Control Bit This read/write bit together with BLK1 allows erasing of blocks of varying size ...
Page 67
... Freescale Semiconductor, Inc. 4.5 FLASH Charge Pump Frequency Control The internal charge pump, required for program, margin read, and erase operations, is designed to operate most efficiently with a 2-MHz clock. The charge pump clock is derived from the bus clock. how the FDIV bits are used to select a charge pump frequency based on the bus clock frequency ...
Page 68
... Freescale Semiconductor, Inc. FLASH-1 Memory 7. Wait for a time Clear the ERASE bit. 9. After time t NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Table 4-2 erase operation. BLK1 In step 2 of the erase operation, the cared addresses are latched and used to determine the location of the block to be erased ...
Page 69
... Freescale Semiconductor, Inc. ordinary read mode except that a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower cell current. Margin read mode imposes a more stringent read condition on the bitcell to ensure the bitcell is programmed with enough margin for long-term data retention ...
Page 70
... Freescale Semiconductor, Inc. FLASH-1 Memory This program/margin read sequence is repeated throughout the memory until all data is programmed. The smart programming algorithm shown in Figure 4-2 array. This algorithm ensures the minimum possible program time and avoids the deleterious program disturb effect. (See Operation ...
Page 71
... Freescale Semiconductor, Inc. Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH 2TS. Note: This page program algorithm assumes the page programmed are initially erased. MC68HC908AS60 — Rev. 1.0 For More Information On This Product, CLEAR MARGIN BIT INCREMENT ATTEMPT COUNTER ...
Page 72
... Freescale Semiconductor, Inc. FLASH-1 Memory 4.8.1 FLASH-1 Block Protect Register The block protect register (FLBPR1) is implemented as a byte within the FLASH-1 memory. Each bit, when programmed, protects a range of addresses in the FLASH-1 array. Address: Read: Write: Reset: BPR3 — Block Protect Register Bit 3 This bit protects the FLASH memory contents in the address range $C000– ...
Page 73
... Freescale Semiconductor, Inc. By programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. Programming more than one bit at a time is redundant. If both bit 1 and bit 2 are set, for instance, the address range $9000–$FFFF is locked. If all bits are erased, then all of the memory is available for erase and program ...
Page 74
... Freescale Semiconductor, Inc. FLASH-1 Memory BPR2 — Block Protect Register Bit 2 This bit protects the FLASH memory contents in the address range $2000–$7FFF. BPR1 — Block Protect Register Bit 1 This bit protects the FLASH memory contents in the address range $1000–$7FFF. ...
Page 75
... Freescale Semiconductor, Inc. 4.9 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 4.9.1 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will be no memory activity since the CPU is inactive ...
Page 76
... Freescale Semiconductor, Inc. FLASH-1 Memory Technical Data FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 ...
Page 77
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 5.1 Contents 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.10.1 5.10.2 5.2 Introduction This section describes the operation of the embedded FLASH-2 memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AS60 — ...
Page 78
... Freescale Semiconductor, Inc. FLASH-2 Memory 5.3 Functional Description The FLASH-2 memory is an array 29,616 bytes. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program and erase operations are facilitated through control bits in a memory mapped register. Details for these operations appear later in this section. Memory in the FLASH array is organized into pages within rows ...
Page 79
... Freescale Semiconductor, Inc. Programming tools are available from Motorola. Contact a local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents. 5.4 FLASH Control Register The FLASH-2 control register (FLCR2) controls FLASH-2 program, erase, and margin read operations. ...
Page 80
... Freescale Semiconductor, Inc. FLASH-2 Memory BLK0 — Block Erase Control Bit This read/write bit together with BLK1 allows erasing of blocks of varying size. See available block sizes. HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array ...
Page 81
... Freescale Semiconductor, Inc. 5.5 FLASH Charge Pump Frequency Control The internal charge pump, required for program, margin read, and erase operations, is designed to operate most efficiently with a 2-MHz clock. The charge pump clock is derived from the bus clock. how the FDIV bits are used to select a charge pump frequency based on the bus clock frequency ...
Page 82
... Freescale Semiconductor, Inc. FLASH-2 Memory 7. Wait for a time Clear the ERASE bit. 9. After a time, t NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Table 5-2 erase operation. BLK1 In step 2 of the erase operation, the cared addresses are latched and used to determine the location of the block to be erased ...
Page 83
... Freescale Semiconductor, Inc. While performing a margin read, the operation is the same as for ordinary read mode except that a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower cell current. Margin read mode imposes a more stringent read condition on the bitcell to ensure the bitcell is programmed with enough margin for long-term data retention ...
Page 84
... Freescale Semiconductor, Inc. FLASH-2 Memory This program/margin read sequence is repeated throughout the memory until all data is programmed. The smart programming algorithm shown in Figure 5-2 array. This algorithm ensures the minimum possible program time and avoids the deleterious program disturb effect. See Operation ...
Page 85
... Freescale Semiconductor, Inc. Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH 2TS. Note: This page program algorithm assumes the page programmed are initially erased. MC68HC908AS60 — Rev. 1.0 For More Information On This Product, CLEAR MARGIN BIT INCREMENT ATTEMPT COUNTER ...
Page 86
... Freescale Semiconductor, Inc. FLASH-2 Memory 5.9 FLASH Block Protect Register The block protect register for FLASH-2 is physically implemented as a byte within the FLASH-1 memory. Refer to Protect Register (FLBPR2) programmed, protects a range of addresses in the FLASH-2 array. 5.10 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes ...
Page 87
... Freescale Semiconductor, Inc. HVEN = 1), then it will remain in that mode during wait. Exit from stop must now be done with a reset rather than an interrupt because if exiting stop with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. ...
Page 88
... Freescale Semiconductor, Inc. FLASH-2 Memory Technical Data FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 ...
Page 89
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 6.1 Contents 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.5 6.5.1 6.5.2 6.2 Introduction This section describes the electrically erasable programmable read-only memory (EEPROM). The 1024 bytes available on the MC68HC908AS60 are physically located in two 512-byte arrays. This section details the array covering the address range $0800– ...
Page 90
... Freescale Semiconductor, Inc. EEPROM-1 6.3 Features EEPROM features include: • • • • • • 6.4 Functional Description The 512 bytes of EEPROM-1 can be programmed or erased without an external voltage supply. EEPROM cells are protected with a non-volatile block protection option. These options are stored in the EEPROM non-volatile register (EENVR1) and are loaded into the EEPROM array configuration register after reset (EEACR1 read of EENVR1 ...
Page 91
... Freescale Semiconductor, Inc. Follow this step-by-step procedure to program a byte of EEPROM: 1. Clear EERAS1 and EERAS0 and set EELAT in the EECR1. (See 2. Write the desired data to any user EEPROM address. 3. Set the EEPGM bit. (See note c.) 4. Wait for a time Clear EEPGM bit. ...
Page 92
... Freescale Semiconductor, Inc. EEPROM-1 6.4.2 EEPROM Erasing The unprogrammed state is a logic 1. Only the valid EEPROM bytes in the non-protected blocks and EENVR1 can be erased. When the array is configured in the redundant mode, erasing the first 256 bytes also will erase the last 256 bytes. ...
Page 93
... Freescale Semiconductor, Inc. b. The EEPGM bit cannot be set if the EELAT bit is cleared and a c. Any attempt to clear both EEPGM and EELAT bits with a single In general, all bits should be erased before being programmed. However, if program/erase cycling is of concern, minimize bit cycling in each EEPROM byte. If any bit in a byte requires change from the byte needs to be erased before programming ...
Page 94
... Freescale Semiconductor, Inc. EEPROM-1 6.4.3 EEPROM Block Protection The 512 bytes of EEPROM are divided into four 128-byte blocks. Each of these blocks can be separately protected by EEBPx bit. Any attempt to program or erase memory locations within the protected block will not allow the program/erase voltage to be applied to the array. ...
Page 95
... Freescale Semiconductor, Inc. The EEPROM non-volatile register (EENVR1) contains configurations concerning block protection and redundancy. EENVR1 is physically located on the bottom of the EEPROM array. The contents are non-volatile and are not modified by reset. On reset, this special register loads the EEPROM configuration into a corresponding volatile EEPROM array configuration register (EEACR1) ...
Page 96
... Freescale Semiconductor, Inc. EEPROM-1 In addition to the disabling of the program and erase operations on memory locations $08F0–$08FF, the enabling of the protect option has the following effects: • • • • • NOTE: Once armed, the protect option is permanently enabled consequence, all functions in the EENVR will remain in the state they were in immediately before the security was enabled ...
Page 97
... Freescale Semiconductor, Inc. NOTE recommended that the internal RC oscillator be used to drive the internal charge pump for applications that have a bus frequency of less than 8 MHz. EEOFF — EEPROM Power Down Bit This read/write bit disables the EEPROM module for lower power consumption. Any attempts to access the array will give unpredictable results ...
Page 98
... Freescale Semiconductor, Inc. EEPROM-1 EEPGM — EEPROM Program/Erase Enable Bit This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset clears the EEPGM bit. ...
Page 99
... Freescale Semiconductor, Inc. EERA — EEPROM Redundant Array Bit This programmable/erasable/read bit in EENVR1 and read-only bit in EEACR1 configures the array in redundant mode. Reset loads EERA from EENVR1 to EEACR1. CON2 and CON1 — MCU Configuration Bits These read/write bits can be used to enable/disable functions within the MCU ...
Page 100
... Freescale Semiconductor, Inc. EEPROM-1 6.5 Low-Power Modes The WAIT and STOP instructions can put the MCU in low power- consumption standby modes. 6.5.1 Wait Mode The WAIT instruction does not affect the EEPROM possible to program the EEPROM and put the MCU in wait mode. However, if the EEPROM is inactive, power can be reduced by setting the EEOFF bit before executing the WAIT instruction ...
Page 101
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 7.1 Contents 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.5 7.5.1 7.5.2 7.2 Introduction This section describes the electrically erasable programmable read-only memory (EEPROM-2) covering the address range $0600–$07FF. ...
Page 102
... Freescale Semiconductor, Inc. EEPROM-2 7.3 Features EEPROM-2 features include: • • • • • • 7.4 Functional Description The 512 bytes of EEPROM-2 can be programmed or erased without an external voltage supply. EEPROM cells are protected with a non-volatile block protection option. These options are stored in the EEPROM non-volatile register (EENVR2) and are loaded into the EEPROM array configuration register after reset (EEACR2 read of EENVR2 ...
Page 103
... Freescale Semiconductor, Inc. Follow this step-by-step procedure to program a byte of EEPROM: 1. Clear EERAS1 and EERAS0 and set EELAT in the EECTL. Set 2. Write the desired data to any user EEPROM address. 3. Set the EEPGM bit. (See note c.) 4. Wait for a time Clear EEPGM bit. ...
Page 104
... Freescale Semiconductor, Inc. EEPROM-2 7.4.2 EEPROM Erasing The unprogrammed state is a logic 1. Only the valid EEPROM bytes in the non-protected blocks and EENVR2 can be erased. When the array is configured in the redundant mode, erasing the first 256 bytes also will erase the last 256 bytes. ...
Page 105
... Freescale Semiconductor, Inc. b. The EEPGM bit cannot be set if the EELAT bit is cleared and a c. Any attempt to clear both EEPGM and EELAT bits with a single In general, all bits should be erased before being programmed. However, if program/erase cycling is of concern, minimize bit cycling in each EEPROM byte. If any bit in a byte requires change from the byte needs be erased before programming ...
Page 106
... Freescale Semiconductor, Inc. EEPROM-2 7.4.3 EEPROM Block Protection The 512 bytes of EEPROM are divided into four 128-byte blocks. Each of these blocks can be separately protected by EEBPx bit. Any attempt to program or erase memory locations within the protected block will not allow the program/erase voltage to be applied to the array. ...
Page 107
... Freescale Semiconductor, Inc. The EEPROM non-volatile register (EENVR2) contains configurations concerning block protection and redundancy. EENVR2 is physically located on the bottom of the EEPROM array. The contents are non-volatile and are not modified by reset. On reset, this special register loads the EEPROM configuration into a corresponding volatile EEPROM array configuration register (EEACR2) ...
Page 108
... Freescale Semiconductor, Inc. EEPROM-2 In addition to the disabling of the program and erase operations on memory locations $06F0–$06FF, the enabling of the protect option has the following effects: • • • • • NOTE: Once armed, the security option is permanently enabled consequence, all functions in the EENVR will remain in the state they were in immediately before the security was enabled ...
Page 109
... Freescale Semiconductor, Inc. NOTE recommended that the internal RC oscillator be used to drive the internal charge pump for applications that have a bus frequency of less than 8 MHz. EEOFF — EEPROM Power Down Bit This read/write bit disables the EEPROM module for lower power consumption. Any attempts to access the array will give unpredictable results ...
Page 110
... Freescale Semiconductor, Inc. EEPROM-2 EEPGM — EEPROM Program/Erase Enable Bit This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset clears the EEPGM bit. ...
Page 111
... Freescale Semiconductor, Inc. EERA — EEPROM Redundant Array Bit This programmable/erasable/read bit in EENVR2 and read-only bit in EEACR2 configures the array in redundant mode. Reset loads EERA from EENVR2 to EEACR2. CON2 and CON1 — MCU Configuration Bits These read/write bits can be used to enable/disable functions within the MCU ...
Page 112
... Freescale Semiconductor, Inc. EEPROM-2 7.5 Low-Power Modes The WAIT and STOP instructions can put the MCU in low power-consumption standby modes. 7.5.1 Wait Mode The WAIT instruction does not affect the EEPROM possible to program the EEPROM and put the MCU in wait mode. However, if the EEPROM is inactive, power can be reduced by setting the EEOFF bit before executing the WAIT instruction ...
Page 113
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 8.1 Contents 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.6.1 8.6.2 8.7 8.8 8.9 8.2 Introduction This section describes the central processor unit (CPU08). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU ...
Page 114
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 8.3 Features Features of the CPU08 include: • • • • • • • • • • • Technical Data Full upward, object-code compatibility with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-bit index register with X-register manipulation instructions 8 ...
Page 115
... Freescale Semiconductor, Inc. 8.4 CPU Registers Figure 8-1 the memory map. MC68HC908AS60 — Rev. 1.0 For More Information On This Product, shows the five CPU registers. CPU registers are not part Figure 8-1. CPU Registers Central Processor Unit (CPU) Go to: www.freescale.com Central Processor Unit (CPU) ...
Page 116
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 8.4.1 Accumulator (A) The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: 8.4.2 Index Register (H:X) The 16-bit index register allows indexed addressing of a 64-Kbyte memory space ...
Page 117
... Freescale Semiconductor, Inc. 8.4.3 Stack Pointer (SP) The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least-significant byte to $FF and does not affect the most-significant byte ...
Page 118
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 8.4.4 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched ...
Page 119
... Freescale Semiconductor, Inc. 8.4.5 Condition Code Register (CCR) The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. Read: Write: Reset Indeterminate V — Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs ...
Page 120
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) NOTE: To maintain M6805 compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first ...
Page 121
... Freescale Semiconductor, Inc. 8.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about CPU architecture. ...
Page 122
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 8.7 CPU During Break Interrupts If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. See counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode). ...
Page 123
... Freescale Semiconductor, Inc. Table 8-1. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with Carry ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X Add without Carry ...
Page 124
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 8-1. Instruction Set Summary (Sheet Source Operation Form Branch if Carry Bit Set BCS rel (Same as BLO) BEQ rel Branch if Equal Branch if Greater Than or BGE opr Equal To (Signed Operands) Branch if Greater Than (Signed BGT opr ...
Page 125
... Freescale Semiconductor, Inc. Table 8-1. Instruction Set Summary (Sheet Source Operation Form BRN rel Branch Never BRSET n,opr,rel Branch if Bit Set BSET n,opr Set Bit BSR rel Branch to Subroutine CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel ...
Page 126
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 8-1. Instruction Set Summary (Sheet Source Operation Form COM opr COMA COMX Complement (One’s COM opr,X Complement) COM ,X COM opr,SP CPHX #opr Compare H:X with M CPHX opr CPX #opr CPX opr CPX opr ...
Page 127
... Freescale Semiconductor, Inc. Table 8-1. Instruction Set Summary (Sheet Source Operation Form JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X ...
Page 128
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 8-1. Instruction Set Summary (Sheet Source Operation Form NEG opr NEGA NEGX Negate (Two’s Complement) NEG opr,X NEG ,X NEG opr,SP NOP No Operation NSA Nibble Swap A ORA #opr ORA opr ORA opr ORA opr,X ...
Page 129
... Freescale Semiconductor, Inc. Table 8-1. Instruction Set Summary (Sheet Source Operation Form SBC #opr SBC opr SBC opr SBC opr,X Subtract with Carry SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC Set Carry Bit SEI Set Interrupt Mask STA opr STA opr ...
Page 130
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 8-1. Instruction Set Summary (Sheet Source Operation Form TST opr TSTA TSTX Test for Negative or Zero TST opr,X TST ,X TST opr,SP TSX Transfer SP to H:X TXA Transfer TXS Transfer H Accumulator C Carry/borrow bit CCR ...
Page 131
... Freescale Semiconductor, Inc. MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Central Processor Unit (CPU) Go to: www.freescale.com Central Processor Unit (CPU) Opcode Map Technical Data ...
Page 132
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 ...
Page 133
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 9. System Integration Module (SIM) 9.1 Contents 9.2 9.3 9.3.1 9.3.2 9.3.3 9.4 9.4.1 9.4.2 9.4.2.1 9.4.2.2 9.4.2.3 9.4.2.4 9.4.2.5 9.5 9.5.1 9.5.2 9.5.3 9.6 9.6.1 9.6.1.1 9.6.1.2 9.6.2 9.6.3 9.6.4 9.7 9.7.1 9.7.2 MC68HC908AS60 — ...
Page 134
... Freescale Semiconductor, Inc. System Integration Module (SIM) 9.8 9.8.1 9.8.2 9.8.3 9.2 Introduction This section describes the system integration module (SIM), which supports external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all MCU activities. The SIM is a system state controller that coordinates CPU and exception timing ...
Page 135
... Freescale Semiconductor, Inc. RESET PIN LOGIC RESET PIN CONTROL SIM RESET STATUS REGISTER MC68HC908AS60 — Rev. 1.0 For More Information On This Product, STOP/WAIT CONTROL SIM COUNTER 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET CONTROL RESET INTERRUPT CONTROL AND PRIORITY DECODE Figure 9-1 ...
Page 136
... Freescale Semiconductor, Inc. System Integration Module (SIM) Addr. Register Name SIM Break Status Register $FE00 (SBSR) See page 151. SIM Reset Status Register $FE01 (SRSR) See page 153. SIM Break Flag Control $FE03 Register (SBFCR) See page 154. Note: Writing a logic 0 clears SBSW. ...
Page 137
... Freescale Semiconductor, Inc. 9.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in from either an external oscillator or from the on-chip phase-locked loop (PLL) ...
Page 138
... Freescale Semiconductor, Inc. System Integration Module (SIM) 9.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles ...
Page 139
... Freescale Semiconductor, Inc. 9.4.1 External Pin Reset Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See ...
Page 140
... Freescale Semiconductor, Inc. System Integration Module (SIM) IRST CGMXCLK 9.4.2.1 Power-On Reset (POR) When power is first applied to the MCU, the POR generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Another 64 CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur ...
Page 141
... Freescale Semiconductor, Inc. OSC1 PORRST 4096 CYCLES CGMXCLK CGMOUT RST IAB 9.4.2.2 Computer Operating Properly (COP) Reset The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR) if the COPD bit in the CONFIG-1 register is at logic 0. See Properly (COP) 9 ...
Page 142
... Freescale Semiconductor, Inc. System Integration Module (SIM) indexed addressing and PUL/PSH instructions will also generate an illegal address reset. WARNING: Extra care should be exercised when using this emulator part for development of code to be run in ROM-based M68HC08AS Family parts with a smaller memory size since some legal addresses will become illegal addresses on the smaller ROM memory map device and may result, generate unwanted resets ...
Page 143
... Freescale Semiconductor, Inc. 9.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the CONFIG-1 register ...
Page 144
... Freescale Semiconductor, Inc. System Integration Module (SIM) Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared) ...
Page 145
... Freescale Semiconductor, Inc. BREAK INTERRUPT? YES AS MANY INTERRUPTS AS EXIST ON CHIP MC68HC908AS60 — Rev. 1.0 For More Information On This Product, FROM RESET YES I BIT SET BIT SET? NO YES IRQ1 INTERRUPT? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES ...
Page 146
... Freescale Semiconductor, Inc. System Integration Module (SIM) 9.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing ...
Page 147
... Freescale Semiconductor, Inc. 9.6.2 Reset All reset sources always have higher priority than interrupts and cannot be arbitrated. 9.6.3 Break Interrupts The break module can stop normal program flow at a software- programmable break point by asserting its break interrupt output. See Section 12. Break by forcing it to the SWI vector location ...
Page 148
... Freescale Semiconductor, Inc. System Integration Module (SIM) Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — ...
Page 149
... Freescale Semiconductor, Inc. IAB IDB R/W Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. IAB IDB EXITSTOPWAIT Note: EXITSTOPWAIT = CGMXCLK 9.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode ...
Page 150
... Freescale Semiconductor, Inc. System Integration Module (SIM) The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG-1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 ...
Page 151
... Freescale Semiconductor, Inc. 9.8 SIM Registers The SIM has three memory mapped registers: • • • 9.8.1 SIM Break Status Register The SIM break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: Read: Write: Reset: SBSW — ...
Page 152
... Freescale Semiconductor, Inc. System Integration Module (SIM) ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE EQU 5 LOBYTE EQU not SBSW, do RTI BRCLR SBSW,SBSR, RETURN ...
Page 153
... Freescale Semiconductor, Inc. 9.8.2 SIM Reset Status Register This register contains six flags that show the source of the last reset. The status register will automatically clear after reading it. A power-on reset sets the POR bit and clears all other bits in the register. ...
Page 154
... Freescale Semiconductor, Inc. System Integration Module (SIM) 9.8.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU break state. Address: Read: Write: Reset: BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU break state ...
Page 155
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 10. Clock Generator Module (CGM) 10.1 Contents 10.2 10.3 10.4 10.4.1 10.4.2 10.4.2.1 10.4.2.2 10.4.2.3 10.4.2.4 10.4.2.5 10.4.3 10.4.4 10.5 10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 10.5.6 10.5.7 10.5.8 10.6 10.6.1 10.6.2 10.6.3 10.7 MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Introduction ...
Page 156
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) 10.8 10.8.1 10.8.2 10.9 10.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 176 10.10.1 Acquisition/Lock Time Definitions 176 10.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .177 10.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 178 10.2 Introduction The clock generator module (CGM) generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal ...
Page 157
... Freescale Semiconductor, Inc. 10.4 Functional Description The CGM consists of three major submodules: 1. Crystal oscillator circuit — The crystal oscillator circuit generates 2. Phase-locked loop (PLL) — The PLL generates the 3. Base clock selector circuit — This software-controlled circuit Figure 10-1 10.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal ...
Page 158
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) OSC1 CGMRDV CGMRCLK V DDA PHASE DETECTOR LOCK DETECTOR LOCK CGMVDV Technical Data CLOCK SELECT CIRCUIT BCS CGMXFC V SS VRS7–VRS4 VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG BANDWIDTH INTERRUPT CONTROL CONTROL AUTO ACQ PLLIE PLLF MUL7– ...
Page 159
... Freescale Semiconductor, Inc. Addr. Register Name PLL Control Register $001C (PCTL) See page 169. PLL Bandwidth Control $001D Register (PBWC) See page 171. PLL Programming Register $001E (PPG) See page 173. Figure 10-2. I/O Register Summary 10.4.2 Phase-Locked Loop Circuit (PLL) ...
Page 160
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f Modulating the voltage on the CGMXFC pin changes the frequency within this range ...
Page 161
... Freescale Semiconductor, Inc. 10.4.2.2 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: 1. Acquisition mode — In acquisition mode, the filter can make large 2. Tracking mode — In tracking mode, the filter makes only small 10.4.2.3 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically ...
Page 162
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) These conditions apply when the PLL is in automatic bandwidth control mode: • • • • • The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation ...
Page 163
... Freescale Semiconductor, Inc. 10.4.2.4 Programming the PLL Use this 9-step procedure to program the PLL. variables used and their meaning. 1. Choose the desired bus frequency Calculate the desired VCO frequency Using a reference frequency Calculate the VCO frequency, f MC68HC908AS60 — Rev. 1.0 For More Information On This Product, Table 10-1 ...
Page 164
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) 5. Calculate the bus frequency the calculated f 7. Using the value 4.9152 MHz for f 8. Calculate the VCO center-of-range frequency, f NOTE: For proper operation, Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. ...
Page 165
... Freescale Semiconductor, Inc. 10.4.2.5 Special Programming Exceptions The programming method, described in PLL, does not account for two possible exceptions. A value of 0 for meaningless when used in the equations given. To account for these exceptions: • • 10.4.3 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT ...
Page 166
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) 10.4.4 CGM External Connections In its typical configuration, the CGM requires seven external components. Five of these are for the crystal oscillator and two are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator ...
Page 167
... Freescale Semiconductor, Inc. SIMOSCEN *R can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. S 10.5 I/O Signals The following paragraphs describe the CGM input/output (I/O) signals. 10.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. ...
Page 168
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) 10.5.4 Analog Power Pin (V V DDA V DDA NOTE: Route V capacitors as close as possible to the package. 10.5.5 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal enables the oscillator and PLL. 10.5.6 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed ...
Page 169
... Freescale Semiconductor, Inc. 10.6 CGM Registers Three registers control and monitor operation of the CGM: 1. PLL control register (PCTL) 2. PLL bandwidth control register (PBWC) 3. PLL programming register (PPG) 10.6.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit ...
Page 170
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) NOTE: Do not inadvertently clear the PLLF bit. Be aware that any read or read-modify-write operation on the PLL control register clears the PLLF bit. PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK ...
Page 171
... Freescale Semiconductor, Inc. 10.6.2 PLL Bandwidth Control Register The PLL bandwidth control register (PBWC): • • • • Address: Read: Write: Reset: AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. LOCK — ...
Page 172
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) ACQ — Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode ...
Page 173
... Freescale Semiconductor, Inc. 10.6.3 PLL Programming Register The PLL programming register (PPG) contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO. Address: Read: Write: Reset: MUL7–MUL4 — Multiplier Select Bits These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier, N ...
Page 174
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) VRS7–VRS4 — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency, f VRS 10.6.1 PLL Control the PLLON bit in the PLL control register (PCTL) is set. See Special Programming select bits disables the PLL and clears the BCS bit in the PCTL ...
Page 175
... Freescale Semiconductor, Inc. service routines from impeding software performance or from exceeding stack limitations. NOTE: Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit. ...
Page 176
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit ...
Page 177
... Freescale Semiconductor, Inc. a certain tolerance of the desired frequency regardless of the size of the initial error. The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical PLL. Therefore, the definitions for acquisition and lock times for this module are: • • ...
Page 178
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency f Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor ...
Page 179
... Freescale Semiconductor, Inc. For acceptable values of C value of V operating. If the power supply is variable, choose a value near the middle of the range of possible supply values. This equation does not always yield a commonly available capacitor size, so round to the nearest available size. If the value is between two different sizes, choose the higher value for better stability ...
Page 180
... Freescale Semiconductor, Inc. Clock Generator Module (CGM) Technical Data Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 ...
Page 181
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 Section 11. Configuration Register (CONFIG-1) 11.1 Contents 11.2 11.3 11.2 Introduction This section describes the configuration register (CONFIG-1), which contains bits that configure these options: • • • • • • 11.3 Functional Description The configuration register is a write-once register. Out of reset, the configuration register will read the default value ...
Page 182
... Freescale Semiconductor, Inc. Configuration Register (CONFIG-1) Address: Read: Write: Reset: Figure 11-1. Configuration Write-Once Register (CONFIG-1) LVISTOP — LVI Stop Mode Enable Bit LVISTOP enables the LVI module in stop mode. See Low-Voltage Inhibit (LVI) NOTE: To have the LVI enabled in stop mode, the LVIPWR must logic 1 and the LVISTOP bit must logic 1 ...
Page 183
... Freescale Semiconductor, Inc. SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. See 9.7.2 Stop NOTE: If using an external crystal oscillator, do not set the SSREC bit. COPL — COP Long Timeout Bit COPL enables the shorter COP timeout period ...
Page 184
... Freescale Semiconductor, Inc. Configuration Register (CONFIG-1) The bit in the CONFIG register or MOR (mask option register) used to control the short and long COP timeout has some variation within the A-Family of devices. CONFIG or MOR of a FLASH or ROM device, respectively. MC68HC908AS60 MC68HC908AZ60 MC68HC08AS32 MC68HC08AS20 ...
Page 185
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 12.1 Contents 12.2 12.3 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.5 12.5.1 12.5.2 12.6 12.6.1 12.6.2 12.2 Introduction The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. ...
Page 186
... Freescale Semiconductor, Inc. Break Module 12.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction ...
Page 187
... Freescale Semiconductor, Inc. Addr. Register Name Break Address Register High $FE0C (BRKH) See page 190. Break Address Register Low $FE0D (BRKL) See page 190. Break Status and Control $FE0E Register (BSCR) See page 189. Figure 12-2. I/O Register Summary 12.4.1 Flag Protection During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state ...
Page 188
... Freescale Semiconductor, Inc. Break Module 12.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when V RST pin. 12.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 12.5.1 Wait Mode If enabled, the break module is active in wait mode. The SIM break stop/wait bit (SBSW) in the SIM break status register indicates whether wait was exited by a break interrupt ...
Page 189
... Freescale Semiconductor, Inc. 12.6.1 Break Status and Control Register The break status and control register (BSCR) contains break module enable and status bits. Address: Read: Write: Reset: Figure 12-3. Break Status and Control Register (BSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. ...
Page 190
... Freescale Semiconductor, Inc. Break Module 12.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Register Name and Address: BRKH — $FE0C Read: Write: Reset: Register Name and Address: BRKL — ...
Page 191
... Freescale Semiconductor, Inc. Technical Data — MC68HC908AS60 13.1 Contents 13.2 13.3 13.4 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 13.4.6 13.4.7 13.2 Introduction This section describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. ...
Page 192
... Freescale Semiconductor, Inc. Monitor ROM (MON) 13.3 Features Features of the monitor ROM include: • • • • • • • 13.4 Functional Description Monitor ROM receives and executes commands from a host computer. Figure 13-1 communicate with a host computer via a standard RS-232 interface. ...
Page 193
... Freescale Semiconductor, Inc. 1 MC145407 + DB- Notes: Position A — Bus clock = CGMXCLK 4 or CGMVCLK Position B — Bus clock = CGMXCLK MC68HC908AS60 — Rev. 1.0 For More Information On This Product MC74HC125 Figure 13-1. Monitor Mode Circuit Monitor ROM (MON) Go to: www.freescale.com Monitor ROM (MON) Functional Description ...
Page 194
... Freescale Semiconductor, Inc. Monitor ROM (MON) 13.4.1 Entering Monitor Mode Table 13 For V Enter monitor mode by either: • • Once out of reset, the MCU waits for the host to send eight security bytes (see signal (10 consecutive logic 0s) to the host computer, indicating that it is ready to receive a command ...
Page 195
... Freescale Semiconductor, Inc. Table 13-2 monitor mode. Modes User Monitor 1. If the high voltage (V its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register. See 13.4.2 Data Format Communication with the MON is in standard non-return-to-zero (NRZ) mark/space data format ...
Page 196
... Freescale Semiconductor, Inc. Monitor ROM (MON) 13.4.3 Echoing As shown in byte back to the PTA0 pin for error checking. Any result of a command appears after the echo of the last byte of the command. SENT TO MONITOR READ ECHO 13.4.4 Break Signal A start bit followed by nine low bits is a break signal. See When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal ...
Page 197
... Freescale Semiconductor, Inc. 13.4.5 Commands The monitor ROM uses these commands: • • • • • • A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 13-3. READ (Read Memory) Command Description Read byte from memory ...
Page 198
... Freescale Semiconductor, Inc. Monitor ROM (MON) Table 13-5. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO MONITOR ...
Page 199
... Freescale Semiconductor, Inc. Table 13-8. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence 13.4.6 Baud Rate With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. If the PTC3 pin is at logic 0 during reset, the monitor baud rate is 9600 ...
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... Freescale Semiconductor, Inc. Monitor ROM (MON) NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. If FLASH is unprogrammed, the eight security byte values to be sent are $FF, the unprogrammed state of FLASH. ...