MC68HC11E1CFN2 Freescale Semiconductor, MC68HC11E1CFN2 Datasheet - Page 121

no-image

MC68HC11E1CFN2

Manufacturer Part Number
MC68HC11E1CFN2
Description
IC MCU 512 EEPROM 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFN2
Manufacturer:
FENGHUA
Quantity:
460 000
Part Number:
MC68HC11E1CFN2
Manufacturer:
MOT
Quantity:
2 600
Part Number:
MC68HC11E1CFN2
Quantity:
5 510
Part Number:
MC68HC11E1CFN2
Manufacturer:
MOTOROLA
Quantity:
9
Part Number:
MC68HC11E1CFN2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC11E1CFN2
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
MC68HC11E1CFN2R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
7.5.2 Address-Mark Wakeup
7.6 SCI Error Detection
M68HC11E Family — Rev. 5
MOTOROLA
The serial characters in this type of wakeup consist of seven (eight if M = 1)
information bits and an MSB, which indicates an address character (when set to 1,
or mark). The first character of each message is an addressing character (MSB =
1). All receivers in the system evaluate this character to determine if the remainder
of the message is directed toward this particular receiver. As soon as a receiver
determines that a message is not intended for it, the receiver activates the RWU
function by using a software write to set the RWU bit. Because setting RWU inhibits
receiver-related flags, there is no further software overhead for the rest of this
message.
When the next message begins, its first character has its MSB set, which
automatically clears the RWU bit and enables normal character reception. The first
character whose MSB is set is also the first character to be received after wakeup
because RWU gets cleared before the stop bit for that frame is serially received.
This type of wakeup allows messages to include gaps of idle time, unlike the
idle-line method, but there is a loss of efficiency because of the extra bit time for
each character (address bit) required for all characters.
Three error conditions – SCDR overrun, received bit noise, and framing – can
occur during generation of SCI system interrupts. Three bits (OR, NF, and FE) in
the serial communications status register (SCSR) indicate if one of these error
conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be transferred from
the receive shift register to the SCDR and the SCDR is already full (RDRF bit is
set). When an overrun error occurs, the data that caused the overrun is lost and
the data that was already in SCDR is not disturbed. The OR is cleared when the
SCSR is read (with OR set), followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits, including
the start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit
is cleared when the SCSR is read (with FE equal to 1) followed by a read of the
SCDR.
When no stop bit is detected in the received data character, the framing error (FE)
bit is set. FE is set at the same time as the RDRF. If the byte received causes both
framing and overrun errors, the processor only recognizes the overrun error. The
framing error flag inhibits further transfer of data into the SCDR until it is cleared.
The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read
of the SCDR.
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Communications Interface (SCI)
Go to: www.freescale.com
Serial Communications Interface (SCI)
SCI Error Detection
Data Sheet
121

Related parts for MC68HC11E1CFN2