MC68HC11E1CFN2 Freescale Semiconductor, MC68HC11E1CFN2 Datasheet - Page 154

no-image

MC68HC11E1CFN2

Manufacturer Part Number
MC68HC11E1CFN2
Description
IC MCU 512 EEPROM 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFN2
Manufacturer:
FENGHUA
Quantity:
460 000
Part Number:
MC68HC11E1CFN2
Manufacturer:
MOT
Quantity:
2 600
Part Number:
MC68HC11E1CFN2
Quantity:
5 510
Part Number:
MC68HC11E1CFN2
Manufacturer:
MOTOROLA
Quantity:
9
Part Number:
MC68HC11E1CFN2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC11E1CFN2
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
MC68HC11E1CFN2R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Timing System
9.4.7 Timer Interrupt Mask 1 Register
9.4.8 Timer Interrupt Flag 1 Register
Data Sheet
154
NOTE:
Use this 8-bit register to enable or inhibit the timer input capture and output
compare interrupts.
OC1I–OC4I — Output Compare x Interrupt Enable Bits
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable Bit
IC1I–IC3I — Input Capture x Interrupt Enable Bits
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Bits in TMSK1 enable
the corresponding interrupt sources.
Bits in this register indicate when timer system events have occurred. Coupled with
the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either
a polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in
TMSK1 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
OC1F–OC4F — Output Compare x Flag
I4/O5F — Input Capture 4/Output Compare 5 Flag
IC1F–IC3F — Input Capture x Flag
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt
sequence is requested.
When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interrupt enable bit.
When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt enable bit.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt
sequence is requested.
Set each time the counter matches output compare x value
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
Set each time a selected active edge is detected on the ICx input line
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
$1022
$1023
OC1F
Figure 9-17. Timer Interrupt Mask 1 Register (TMSK1)
OC1I
Bit 7
Bit 7
Figure 9-18. Timer Interrupt Flag 1 Register (TFLG1)
0
0
Go to: www.freescale.com
OC2F
OC2I
6
0
6
0
Timing System
OC3F
OC3I
5
0
5
0
OC4F
OC4I
4
0
4
0
I4/O5F
I4/O5I
3
0
3
0
IC1F
IC1I
M68HC11E Family — Rev. 5
2
0
2
0
IC2F
IC2I
1
0
1
0
MOTOROLA
Bit 0
Bit 0
IC3F
IC3I
0
0

Related parts for MC68HC11E1CFN2