MC68HC11E1CFN2 Freescale Semiconductor, MC68HC11E1CFN2 Datasheet - Page 41

• Manufacturer Part Number: MC68HC11E1CFN2
• Description: IC MCU 512 EEPROM 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

M68HC11E Family — Rev. 5
MOTOROLA
$101E
$101F
$1020
$1021
$1022
$1023
$1024
$1025
$1026
$1027
$1028
$1029
Addr.
Serial Peripheral Control Register
Serial Peripheral Status Register
Timer Interrupt Mask 1 Register
Timer Interrupt Mask 2 Register
Timer Input Capture 4/Output
Timer Input Capture 4/Output
Pulse Accumulator Control
Compare 5 Register High
Pulse Accumulator Count
Compare 5 Register Low
Register Name
Timer Control Register 1
Timer Control Register 2
(TI4/O5)
(TI4/O5)
Timer Interrupt Flag 1
Timer Interrupt Flag 2
Register (PACNT)
Register (PACTL)
Figure 2-7. Register and Control Bit Assignments (Sheet 4 of 6)
See page 148.
See page 148.
See page 153.
See page 146.
See page 154.
See page 154.
See page 155.
See page 158.
See page 159.
See page 162.
See page 138.
See page 139.
(TMSK1)
(TMSK2)
(TFLG1)
(TFLG2)
(TCTL1)
(TCTL2)
(SPCR)
(SPSR)
Freescale Semiconductor, Inc.
For More Information On This Product,
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Operating Modes and On-Chip Memory
I = Indeterminate after reset
EDG4B
DDRA7
Bit 15
OC1F
Bit 7
Bit 7
OC1I
SPIE
Bit 7
OM2
SPIF
TOF
TOI
Go to: www.freescale.com
1
1
0
0
0
0
0
0
0
0
0
= Unimplemented
EDG4A
Bit 14
WCOL
OC2F
PAEN
Bit 6
OC2I
Bit 6
RTIF
SPE
OL2
RTII
1
1
6
0
0
0
0
0
0
0
0
0
PAMOD
EDG1B
PAOVF
DWOM
Bit 13
PAOVI
OC3F
Bit 5
Bit 5
OC3I
OM3
1
1
5
0
0
0
0
0
0
0
0
0
Indeterminate after reset
PEDGE
EDG1A
Bit 12
MODF
MSTR
OC4F
Bit 4
Bit 4
OC4I
PAIF
OL3
PAII
R
1
1
0
0
0
0
0
0
0
0
0
4
Operating Modes and On-Chip Memory
= Reserved
EDG2B
DDRA3
Bit 11
I4/O5F
I4/O5I
CPOL
Bit 3
Bit 3
OM4
1
1
3
0
0
0
0
0
0
0
0
0
EDG2A
Bit 10
CPHA
U = Unaffected
Bit 2
I4/O5
Bit 2
IC1F
OL4
IC1I
1
1
2
0
0
0
0
0
0
0
1
0
EDG3B
RTR1
SPR1
Bit 9
Bit 1
Bit 1
OM5
IC2F
IC2I
PR1
1
1
U
1
0
0
0
0
0
0
0
0
Memory Map
Data Sheet
EDG3A
RTR0
SPR0
Bit 8
Bit 0
Bit 0
IC3F
Bit 0
OL5
IC3I
PR0
1
1
U
0
0
0
0
0
0
0
0
41