MC68HC11E1CFN2 Freescale Semiconductor, MC68HC11E1CFN2 Datasheet - Page 69

• Manufacturer Part Number: MC68HC11E1CFN2
• Description: IC MCU 512 EEPROM 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

3.8 Operation in Stop and Wait Modes
3.9 A/D Control/Status Register
M68HC11E Family — Rev. 5
MOTOROLA
If a conversion sequence is in progress when either the stop or wait mode is
entered, the conversion of the current channel is suspended. When the MCU
resumes normal operation, that channel is resampled and the conversion
sequence is resumed. As the MCU exits wait mode, the A/D circuits are stable and
valid results can be obtained on the first conversion. However, in stop mode, all
analog bias currents are disabled and it is necessary to allow a stabilization period
when leaving stop mode. If stop mode is exited with a delay (DLY = 1), there is
enough time for these circuits to stabilize before the first conversion. If stop mode
is exited with no delay (DLY bit in OPTION register = 0), allow 10 ms for the A/D
circuitry to stabilize to avoid invalid results.
All bits in this register can be read or written, except bit 7, which is a read-only
status indicator, and bit 6, which always reads as 0. Write to ADCTL to initiate a
conversion. To quit a conversion in progress, write to this register and a new
conversion sequence begins immediately.
CCF — Conversion Complete Flag
Bit 6 — Unimplemented
SCAN — Continuous Scan Control Bit
MULT — Multiple Channel/Single Channel Control Bit
A read-only status indicator, this bit is set when all four A/D result registers
contain valid conversion results. Each time the ADCTL register is overwritten,
this bit is automatically cleared to 0 and a conversion sequence is started. In the
continuous mode, CCF is set at the end of the first conversion sequence.
Always reads 0
When this control bit is clear, the four requested conversions are performed
once to fill the four result registers. When this control bit is set, conversions are
performed continuously with the result registers updated as data becomes
available.
When this bit is clear, the A/D converter system is configured to perform four
consecutive conversions on the single channel specified by the four channel
select bits CD:CA (bits [3:0] of the ADCTL register). When this bit is set, the A/D
Address: $1030
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
CCF
Bit 7
0
Figure 3-5. A/D Control/Status Register (ADCTL)
Analog-to-Digital (A/D) Converter
Go to: www.freescale.com
= Unimplemented
6
0
SCAN
5
MULT
4
Indeterminate after reset
CD
3
Operation in Stop and Wait Modes
Analog-to-Digital (A/D) Converter
CC
2
CB
1
Data Sheet
Bit 0
CA
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