MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 120

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MC68HC711K4CFU4

Manufacturer Part Number
MC68HC711K4CFU4
Description
IC MCU 24K 4MHZ EEPROM 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711K4CFU4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
24KB (24K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC711K4CFU4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Resets and Interrupts
5.5.1 Non-Maskable Interrupts
5.5.1.1 Non-Maskable Interrupt Request (XIRQ)
5.5.1.2 Illegal Opcode Trap
Technical Data
120
Non-maskable interrupts can interrupt CPU operations at any time. The
most common use for such an interrupt is for serious system problems,
such as program runaway or power failure. The three sources of
non-maskable interrupt are:
The XIRQ input is an updated version of the non-maskable NMI input of
earlier MCUs. Upon reset, both the X bit and I bit of the CCR are set to
inhibit all maskable interrupts and XIRQ. After minimum system
initialization, software can clear the X bit by a transfer from accumulator
A to condition code register (TAP) instruction, enabling XIRQ interrupts.
Thereafter, software cannot set the X bit and the XIRQ interrupt
becomes non-maskable.
I bit-related interrupts do not affect the X bit, which has a higher priority
than they do in the interrupt priority logic. When an I bit-related interrupt
occurs, the CPU sets the I bit after stacking the CCR byte, but the X bit
remains unaffected. When an X bit-related interrupt occurs, the CPU
sets both the X and I bits after stacking the CCR. The RTI instruction
restores the X and I bits to their pre-interrupt request state when it pulls
the CCR from the stack.
The MCU includes an illegal opcode detection circuit to avoid attempting
to process undefined opcodes or opcode sequences. This mechanism
works for all unimplemented opcodes on all four opcode map pages.
When the circuit detects an illegal opcode, it generates an interrupt. The
CPU responds by pushing the current value of the program counter,
which is actually the address of the first byte of the illegal opcode, on the
stack. The illegal opcode service routine can use this stacked address
as a pointer to the illegal opcode to correct it. To avoid repeated
Freescale Semiconductor, Inc.
For More Information On This Product,
XIRQ pin
Illegal opcode trap
Software interrupt instruction (SWI)
Go to: www.freescale.com
Resets and Interrupts
M68HC11K Family
MOTOROLA

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