MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 130

• Manufacturer Part Number: MC68HC711K4CFU4
• Description: IC MCU 24K 4MHZ EEPROM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Resets and Interrupts
5.8.1 Wait Mode
5.8.2 Stop Mode
Technical Data
130
The WAI opcode places the MCU in the wait condition, during which the
CPU registers are stacked and CPU processing is suspended until a
qualified interrupt is detected. The interrupt can be an external IRQ, an
XIRQ, or any of the internally generated interrupts, such as the timer or
serial interrupts. The on-chip crystal oscillator remains active throughout
the wait standby period.
The reduction of power in the wait condition depends on how many
internal clock signals driving on-chip peripheral functions can be shut
down. The CPU is always shut down during WAIT. While in the wait
state, the address/data bus repeatedly runs read cycles to the address
where the CCR contents were stacked. The MCU leaves the wait state
when it senses any interrupt that has not been masked.
The free-running timer system is shut down only if maskable interrupts
are disabled (I bit is set) and the COP system is disabled (NOCOP is
set). Other systems can be shut down through the software-controlled
configuration control bits, including the SPI system (SPE control bit), the
SCI transmitter (TE bit), and the SCI receiver (RE bit). Net power
reduction in WAIT depends on which of these features is disabled.
The STOP instruction halts all system clocks, including the crystal
oscillator, thereby minimizing power consumption. The S bit in the CCR
must be cleared to place the MCU in the stop condition; otherwise, the
stop opcode is treated as a no-operation (NOP). To exit STOP and
resume normal processing, a logic low level must be applied to one of
the external interrupt pins (IRQ or XIRQ) or to the RESET pin. A pending
edge-triggered IRQ can also bring the CPU out of stop.
Because all clocks are stopped in this mode, all internal peripheral
functions also stop. RAM and register contents are preserved as long as
V
are not altered by STOP, so the MCU resumes processing seamlessly
after the system is reactivated by an interrupt. However, if a reset is used
DD
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power is maintained. The CPU state and I/O pin levels are static and
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Resets and Interrupts
M68HC11K Family
MOTOROLA