MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 132

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MC68HC711K4CFU4

Manufacturer Part Number
MC68HC711K4CFU4
Description
IC MCU 24K 4MHZ EEPROM 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711K4CFU4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
24KB (24K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC711K4CFU4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Resets and Interrupts
5.8.3 Slow Mode
Technical Data
132
Address: $002E
DLY — Enable Oscillator Startup Delay Bit
Slow mode is a software selectable feature on M68HC(7)11KS devices
that allows the user to connect, under software control, an extra
divide-by-16 between the oscillator and the internal clock. This feature
permits a slow down of all the internal operations reducing power
consumption.
When WAI is used for power reduction, the slow mode helps further
reduce the power. Control of slow mode is performed in the system
configuration options 3 register (OPT3). See
SM — Slow-Mode Enable Bit
Reset:
Read:
Write:
Figure 5-12. System Configuration Options 3 Register (OPT3)
This bit is set during reset and can be written only once during the first
64 E-clock cycles after reset in normal modes. This bit can be used to
inhibit the oscillator startup delay after reset when using an external
clock source.
Read and write at any time
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
1 = When the SM bit is asserted, a 16-clock divider is connected
0 = When the SM bit is negated, the divider is disconnected and the
Bit 7
between the oscillator and the internal clock. This causes the
system clock to run 16 times slower than normal. All modules
of the MCU slow down, including the timer, SCI, SPI, and A/D.
It is also cleared in hardware when entering stop mode or when
reset, including POR, is asserted low.
system runs at normal bus speed.
0
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Resets and Interrupts
SM
6
0
5
0
4
0
3
0
Figure
2
0
5-12.
M68HC11K Family
1
0
MOTOROLA
Bit 0
0

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