MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 150

• Manufacturer Part Number: MC68HC711K4CFU4
• Description: IC MCU 24K 4MHZ EEPROM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Communications Interface (SCI)
7.3 Data Format
Technical Data
150
START
START
BIT
BIT
BIT 0
BIT 0
BIT 1
BIT 1
The M68HC11K series offers several enhancements to the basic
MC68HC11 SCI, including:
The SCI uses the standard non-return to zero mark/space data format
illustrated in
Data is transmitted in frames consisting of a start bit, a word of eight or
nine data bits, and a stop bit. The step-by-step transmission procedure
is:
1. The transmission line is idle before a message is transmitted. This
2. A start bit, logic 0, is transmitted, indicating the start of a frame.
3. An 8-bit or 9-bit word is transmitted, least significant bit (LSB) first.
4. A stop bit, logic 1, is transmitted to indicate the end of a frame.
5. An optional number of breaks can be transmitted. A break is the
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Freescale Semiconductor, Inc.
BIT 2
BIT 2
For More Information On This Product,
13-bit modulus prescaler in the baud generator
Receiver-active flag
Transmitter and receiver hardware parity
Accelerated idle line detection
means that the line is in a logic 1 state for at least one frame time.
transmission of a logic low state for one frame time. After the last
break character is sent, the line goes high for at least one bit time.
Serial Communications Interface (SCI)
Figure 7-1. SCI Data Formats
BIT 3
BIT 3
9-BIT DATA FORMAT
(BIT MIN SCC1 CLEAR)
(BIT MIN SCC1 SET)
8-BIT DATA FORMAT
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Figure
BIT 4
BIT 4
7-1.
BIT 5
BIT5
BIT 6
BIT6
BIT 7
BIT7
OR DATA
PARITY
STOP
BIT
BIT 8
BIT
START
NEXT
STOP
BIT
BIT
START
NEXT
M68HC11K Family
BIT
MOTOROLA