MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 151

• Manufacturer Part Number: MC68HC711K4CFU4
• Description: IC MCU 24K 4MHZ EEPROM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.4 Transmit Operation
M68HC11K Family
MOTOROLA
Transmission starts by writing a data character to the 2-byte SCI data
register (SCDRH and SCDRL). The MCU parallel-loads the character
into a serial shift register which shifts the data out on the transmission
pin. This double-buffered operation allows transmission of the current
character while the MCU loads the next one. The output of the serial shift
register drives the TxD pin as long as the transmit enable (TE) bit of
serial communication control register 2 (SCCR2) is set.
Two flags in serial communication status register 1 (SCSR1) alert the
MCU of transmission status. The TDRE (transmit data register empty)
flag is set when the SCDR loads its contents into the shift register; this
flag can generate an interrupt if the TIE (transmit interrupt enable) bit in
SCCR2 is set. The TC (transmit complete) flag is set when transmission
is complete (line idle); this can also generate an interrupt if the TCIE
(transmit complete interrupt enable) bit in SCSR1 is set. The TDRE and
TC flags are normally set when software sets the TE bit to enable the
transmitter. See
System
If interrupts are not enabled, the status flags can be read by software
(polled) to determine when the corresponding conditions exist. Status
flags are set automatically by hardware logic conditions, but must be
cleared by software. The software clearing sequence for these flags is
automatic. Functions that are normally performed in response to the
status flags also satisfy the conditions of the clearing sequence.
When software clears the TE bit, the TxD pin reverts to its
general-purpose I/O function (PD1). The transmitter completes
transmission of a character in progress before actually shutting down;
other characters waiting in the transmit queue are lost. The TC and
TDRE flags are set at the completion of this last character, even though
TE has been disabled. Only an MCU reset can abort transmission in
midcharacter.
6. Steps 2-5 are repeated until the entire message is sent.
7. The line returns to idle status.
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Communications Interface (SCI)
for a flow diagram of SCI interrupts.
Go to: www.freescale.com
Figure 5-10. Interrupt Priority Resolution Within SCI
Serial Communications Interface (SCI)
Transmit Operation
Technical Data
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