MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 172

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MC68HC711K4CFU4

Manufacturer Part Number
MC68HC711K4CFU4
Description
IC MCU 24K 4MHZ EEPROM 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711K4CFU4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
24KB (24K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC711K4CFU4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Serial Peripheral Interface (SPI)
8.5 SPI System Errors
8.5.1 Mode Fault Error
Technical Data
172
CPOL selects an active high or low clock edge. CPHA selects one of two
transfer formats. When CPHA is cleared, the shift clock is ORed with SS.
Each slave’s SS pin must be pulled high before it writes the next output
byte to its data register. If a slave writes to its data register while SS is
low, a write collision error occurs. When CPHA is set, SS may be left low
for several SPI characters. When there is only one SPI slave MCU, its
SS line may be tied to V
The SPI configuration determines the characteristics of a transfer in
progress. For a master, a transfer begins when data is written to SPDR
and ends when SPIF is set. For a slave with CPHA cleared, a transfer
starts when SS goes low and ends when SS returns high. In this case,
SPIF is set at the middle of the eighth SCK cycle when data is
transferred from the shifter to the parallel data register, but the transfer
is still in progress until SS goes high. For a slave with CPHA set, transfer
begins when the SCK line goes to its active level, which is the edge at
the beginning of the first SCK cycle. The transfer ends when SPIF is set.
SCK in a slave must be inactive for at least two E-clock cycles between
byte transfers.
Two types of errors can be detected by the SPI system:
A mode fault error occurs when the SS input line of an SPI system
configured as a master goes to active low, usually because two devices
have attempted to act as master at the same time. The resulting
contention between push-pull CMOS pin drivers can cause them
permanent damage. The mode fault disables the drivers in an attempt to
protect them. The MSTR control bit in the SPCR and all four DDRD
Freescale Semiconductor, Inc.
For More Information On This Product,
A mode fault error can occur when multiple devices attempt to act
in master mode simultaneously.
A write collision error results from an attempt to write data to the
SPDR while a transmission is in progress.
Serial Peripheral Interface (SPI)
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SS
if CPHA = 1 at all times.
M68HC11K Family
MOTOROLA

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