MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 173

• Manufacturer Part Number: MC68HC711K4CFU4
• Description: IC MCU 24K 4MHZ EEPROM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.5.2 Write Collision Error
8.6 SPI Registers
M68HC11K Family
MOTOROLA
control bits associated with the SPI are cleared, effectively forcing the
pins to be high-impedance inputs. The mode fault error flag (MODF) is
set in the serial peripheral status register (SPSR). An interrupt is
generated, subject to masking by the SPIE control bit and the I bit in the
CCR. To disable the mode fault circuit, write a 1 to DDRD bit 5. This
configures port D bit 5 as a general-purpose output rather than SS.
Other precautions may be necessary to prevent driver damage. For
instance, if two devices are made masters at the same time, mode fault
does not help protect either one unless one of them selects the other as
slave. The amount of damage possible depends on the length of time
both devices attempt to act as master.
A write collision error occurs when the SPDR is written while a
transmission is in progress. The SPDR is not double buffered in the
transmit direction, so writes to the SPDR go directly into the SPI shift
register, which would corrupt any transfer in progress. The MCU protects
against this by preventing the write and generating the write collision
error. The transmission continues undisturbed.
A write collision is normally a slave error because a slave has no control
over when a master initiates a transfer. A master knows when a transfer
is in progress, so there is no reason for a master to generate a
write-collision error, although the SPI logic can detect write collisions in
both master and slave devices.
The three SPI registers provide control, status, and data storage
functions respectively:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Serial peripheral control register (SPCR)
Serial peripheral status register (SPSR)
Serial peripheral data register (SPDR)
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
Serial Peripheral Interface (SPI)
Technical Data
SPI Registers
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