MC68HC711E9CFN2 Freescale Semiconductor, MC68HC711E9CFN2 Datasheet - Page 71

• Manufacturer Part Number: MC68HC711E9CFN2
• Description: IC MCU 12K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Instruction Set
4.5.3 Extended
In the extended addressing mode, the effective address of the argument is contained in two bytes
following the opcode byte. These are 3-byte instructions (or 4-byte instructions if a prebyte is required).
One or two bytes are needed for the opcode and two for the effective address.
4.5.4 Indexed
In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value
contained in an index register (IX or IY). The sum is the effective address. This addressing mode allows
referencing any memory location in the 64-Kbyte address space. These are 2- to 5-byte instructions,
depending on whether or not a prebyte is required.
4.5.5 Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is contained in
the opcode. Operations that use only the index registers or accumulators, as well as control instructions
with no arguments, are included in this addressing mode. These are
1- or 2-byte instructions.
4.5.6 Relative
The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit
signed offset included in the instruction is added to the contents of the program counter to form the
effective branch address. Otherwise, control proceeds to the next instruction. These are usually 2-byte
instructions.
4.6 Instruction Set
Refer to
Table
4-2, which shows all the M68HC11 instructions in all possible addressing modes. For each
instruction, the table shows the operand construction, the number of machine code bytes, and execution
time in CPU E-clock cycles.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
71