MC68HC11E0CFN2 Freescale Semiconductor, MC68HC11E0CFN2 Datasheet - Page 146

• Manufacturer Part Number: MC68HC11E0CFN2
• Description: IC MCU 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Timing System
9.3.1 Timer Control Register 2
9.3.2 Timer Input Capture Registers
Data Sheet
146
Use the control bits of this register to program input capture functions to detect a
particular edge polarity on the corresponding timer input pin. Each of the input
capture functions can be independently configured to detect rising edges only,
falling edges only, any edge (rising or falling), or to disable the input capture
function. The input capture functions operate independently of each other and can
capture the same TCNT value if the input edges are detected within the same timer
count cycle.
EDGxB and EDGxA — Input Capture Edge Control Bits
When an edge has been detected and synchronized, the 16-bit free-running
counter value is transferred into the input capture register pair as a single 16-bit
parallel transfer. Timer counter value captures and timer counter incrementing
occur on opposite half-cycles of the phase 2 clock so that the count value is stable
whenever a capture occurs. The timer input capture registers are not affected by
reset. Input capture values can be read from a pair of 8-bit read-only registers. A
read of the high-order byte of an input capture register pair inhibits a new capture
transfer for one bus cycle. If a double-byte read instruction, such as load double
accumulator D (LDD), is used to read the captured value, coherency is assured.
When a new input capture occurs immediately after a high-order byte read, transfer
is delayed for an additional cycle but the value is not lost.
There are four pairs of these bits. Each pair is cleared to 0 by reset and must be
encoded to configure the corresponding input capture edge detector circuit. IC4
functions only if the I4/O5 bit in the PACTL register is set. Refer to
timer control configuration.
Address:
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
EDG4B
$1021
Bit 7
0
EDGxB
Figure 9-3. Timer Control Register 2 (TCTL2)
Go to: www.freescale.com
0
0
1
1
Table 9-2. Timer Control Configuration
EDG4A
6
0
Timing System
EDGxA
EDG1B
5
0
0
1
0
1
EDG1A
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge
4
0
Configuration
EDG2B
3
0
EDG2A
M68HC11E Family — Rev. 5
2
0
EDG3B
1
0
Table 9-2
MOTOROLA
EDG3A
Bit 0
0
for