MC68HC11E0CFN2 Freescale Semiconductor, MC68HC11E0CFN2 Datasheet - Page 78

• Manufacturer Part Number: MC68HC11E0CFN2
• Description: IC MCU 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Central Processor Unit (CPU)
4.2.6.6 Half Carry (H)
4.2.6.7 X Interrupt Mask (X)
4.2.6.8 STOP Disable (S)
4.3 Data Types
Data Sheet
78
operation of the CPU continues uninterrupted until the I bit is cleared. After any
reset, the I bit is set by default and can only be cleared by a software instruction.
When an interrupt is recognized, the I bit is set after the registers are stacked, but
before the interrupt vector is fetched. After the interrupt has been serviced, a
return-from-interrupt instruction is normally executed, restoring the registers to the
values that were present before the interrupt occurred. Normally, the I bit is 0 after
a return from interrupt is executed. Although the I bit can be cleared within an
interrupt service routine, "nesting" interrupts in this way should only be done when
there is a clear understanding of latency and of the arbitration mechanism. Refer
to
The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic
unit during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half
carry is used during BCD operations.
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is
set by default and must be cleared by a software instruction. When an XIRQ
interrupt is recognized, the X and I bits are set after the registers are stacked, but
before the interrupt vector is fetched. After the interrupt has been serviced, an RTI
instruction is normally executed, causing the registers to be restored to the values
that were present before the interrupt occurred. The X interrupt mask bit is set only
by hardware (RESET or XIRQ acknowledge). X is cleared only by program
instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value
loaded into the CCR from the stack has been cleared). There is no hardware action
for clearing X.
Setting the STOP disable (S) bit prevents the STOP instruction from putting the
M68HC11 into a low-power stop condition. If the STOP instruction is encountered
by the CPU while the S bit is set, it is treated as a no-operation (NOP) instruction,
and processing continues to the next instruction. S is set by reset; STOP is
disabled by default.
The M68HC11 CPU supports four data types:
Section 5. Resets and
1. Bit data
2. 8-bit and 16-bit signed and unsigned integers
3. 16-bit unsigned fractions
4. 16-bit addresses
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Central Processor Unit (CPU)
Interrupts.
M68HC11E Family — Rev. 5
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