MC68HC11E0CFN2 Freescale Semiconductor, MC68HC11E0CFN2 Datasheet - Page 92

• Manufacturer Part Number: MC68HC11E0CFN2
• Description: IC MCU 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Resets and Interrupts
5.2.5 System Configuration Options Register
Data Sheet
92
ADPU — Analog-to-Digital Converter Power-Up Bit
CSEL — Clock Select Bit
IRQE — Configure IRQ for Edge-Sensitive-Only Operation Bit
DLY — Enable Oscillator Startup Delay Bit
CME — Clock Monitor Enable Bit
Bit 2 — Unimplemented
CR[1:0] — COP Timer Rate Select Bit
1. Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes
Refer to
Refer to
Refer to
Analog-to-Digital (A/D)
This control bit can be read or written at any time and controls whether or not
the internal clock monitor circuit triggers a reset sequence when the system
clock is slow or absent. When it is clear, the clock monitor circuit is disabled, and
when it is set, the clock monitor circuit is enabled. Reset clears the CME bit.
Always reads 0
The internal E clock is first divided by 2
system. These control bits determine a scaling factor for the watchdog timer.
See
Address:
Reset:
Read:
Write:
0 = IRQ is configured for level-sensitive operation.
1 = IRQ is configured for edge-sensitive-only operation.
0 = Clock monitor circuit disabled
1 = Slow or stopped clocks cause reset
Freescale Semiconductor, Inc.
Table 5-1
Figure 5-2. System Configuration Options Register (OPTION)
For More Information On This Product,
Section 3. Analog-to-Digital (A/D)
Section 3. Analog-to-Digital (A/D)
Section 2. Operating Modes and On-Chip Memory
$1039
ADPU
Bit 7
0
Go to: www.freescale.com
for specific timeout settings.
= Unimplemented
Resets and Interrupts
CSEL
6
0
Converter.
IRQE
5
0
(1)
DLY
4
1
(1)
15
before it enters the COP watchdog
Converter.
Converter.
CME
3
0
M68HC11E Family — Rev. 5
2
0
CR1
and
1
0
(1)
Section 3.
MOTOROLA
CR0
Bit 0
0
(1)