MC68HC11E0CFN2 Freescale Semiconductor, MC68HC11E0CFN2 Datasheet - Page 94

• Manufacturer Part Number: MC68HC11E0CFN2
• Description: IC MCU 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Resets and Interrupts
5.3.1 Central Processor Unit (CPU)
5.3.2 Memory Map
5.3.3 Timer
5.3.4 Real-Time Interrupt (RTI)
5.3.5 Pulse Accumulator
Data Sheet
94
After reset, the central processor unit (CPU) fetches the restart vector from the
appropriate address during the first three cycles and begins executing instructions.
The stack pointer and other CPU registers are indeterminate immediately after
reset; however, the X and I interrupt mask bits in the condition code register (CCR)
are set to mask any interrupt requests. Also, the S bit in the CCR is set to inhibit
stop mode.
After reset, the INIT register is initialized to $01, mapping the RAM at $00 and the
control registers at $1000.
For the MC68HC811E2, the CONFIG register resets to $FF. EEPROM mapping
bits (EE[3:0]) place the EEPROM at $F800. Refer to the memory map diagram for
MC68HC811E2 in
During reset, the timer system is initialized to a count of $0000. The prescaler bits
are cleared, and all output compare registers are initialized to $FFFF. All input
capture registers are indeterminate after reset. The output compare 1 mask
(OC1M) register is cleared so that successful OC1 compares do not affect any I/O
pins. The other four output compares are configured so that they do not affect any
I/O pins on successful compares. All input capture edge-detector circuits are
configured for capture disabled operation. The timer overflow interrupt flag and all
eight timer function interrupt flags are cleared. All nine timer interrupts are disabled
because their mask bits have been cleared.
The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as
OC5; however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5
does not control the PA3 pin.
The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are
masked. The rate control bits are cleared after reset and can be initialized by
software before the real-time interrupt (RTI) system is used.
The pulse accumulator system is disabled at reset so that the pulse accumulator
input (PAI) pin defaults to being a general-purpose input pin.
Freescale Semiconductor, Inc.
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Section 2. Operating Modes and On-Chip
Resets and Interrupts
M68HC11E Family — Rev. 5
Memory.
MOTOROLA