COP8SAA716N8 National Semiconductor, COP8SAA716N8 Datasheet - Page 20

IC MCU OTP 8BIT 1K 16-DIP

COP8SAA716N8

Manufacturer Part Number
COP8SAA716N8
Description
IC MCU OTP 8BIT 1K 16-DIP
Manufacturer
National Semiconductor
Series
COP8™ 8SAr
Datasheet

Specifications of COP8SAA716N8

Core Processor
COP8
Core Size
8-Bit
Speed
10MHz
Connectivity
Microwire/Plus (SPI)
Peripherals
POR, PWM, WDT
Number Of I /o
12
Program Memory Size
1KB (1K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SAA716N8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
COP8SAA716N8
Manufacturer:
NS/国半
Quantity:
20 000
www.national.com
6.0 Functional Description
6.9 CONTROL REGISTERS
CNTRL Register (Address X'00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
PSW Register (Address X'00EF)
The PSW register contains the following select bits:
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
Reserved
Bit 7
Bit 7
T1C3
Bit 7
HC
T1C3
T1C2
T1C1
T1C0
MSEL
IEDG
SL1 & SL0
HC
C
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
T1ENA
EXPND
BUSY
EXEN
GIE
Reserved This bit is reserved and should to zero
LPEN
T0PND
T0EN
µWPND
µWEN
T1PNDB
C
T1C2
LPEN
T1PNDA
Half Carry Flag
Carry Flag
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
External interrupt pending
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
Global interrupt enable (enables interrupts)
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
MICROWIRE/PLUS interrupt pending
Enable MICROWIRE/PLUS interrupt
Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
T1C1
T0PND
T1ENA
T1C0
T0EN
EXPND
µWPND
MSEL
µWEN
IEDG
BUSY
T1PNDB
(Continued)
SL1
EXEN
T1ENB
SL0
Bit 0
Bit 0
GIE
Bit 0
20
7.0 Timers
The device contains a very versatile set of timers (T0, T1).
Timer T1 and associated autoreload/capture registers power
up containing random data.
7.1 TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0. The Timer
T0 runs continuously at the fixed rate of the instruction cycle
clock, t
which is a count down timer.
The Timer T0 supports the following functions:
• Exit out of the Idle Mode (See Idle Mode description)
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
• Timing the width of the internal power-on-reset
The IDLE Timer T0 can generate an interrupt when the
twelfth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4.096 ms at the maximum
clock frequency (t
interrupt from the twelfth bit of Timer T0 to be enabled or
disabled. Setting T0EN will enable the interrupt, while reset-
ting it will disable the interrupt.
7.2 TIMER T1
One of the main functions of a microcontroller is to provide
timing and counting capability for real-time control tasks. The
COP8 family offers a very versatile 16-bit timer/counter
structure, and two supporting 16-bit autoreload/capture reg-
isters (R1A and R1B), optimized to reduce software burdens
in real-time control applications. The timer block has two pins
associated with it, T1A and T1B. Pin T1A supports I/O re-
quired by the timer block, while pin T1B is an input to the
timer block.
The timer block has three operating modes: Processor Inde-
pendent PWM mode, External Event Counter mode, and
Input Capture mode.
The control bits T1C3, T1C2, and T1C1 allow selection of the
different modes of operation.
7.2.1 Mode 1. Processor Independent PWM Mode
One of the timer’s operating modes is the Processor Inde-
pendent PWM mode. In this mode, the timer generates a
“Processor Independent” PWM signal because once the
timer is setup, no more action is required from the CPU
which translates to less software overhead and greater
throughput. The user software services the timer block only
when the PWM parameters require updating. This capability
is provided by the fact that the timer has two separate 16-bit
reload registers. One of the reload registers contains the
“ON” timer while the other holds the “OFF” time. By contrast,
a microcontroller that has only a single reload register re-
quires an additional software to update the reload value
(alternate between the on-time/off-time).
The timer can generate the PWM output with the width and
duty cycle controlled by the values stored in the reload
registers. The reload registers control the countdown values
and the reload values are automatically written into the timer
when it counts down through 0, generating interrupt on each
reload. Under software control and with minimal overhead,
T1ENB
C
. The user cannot read or write to the IDLE Timer T0,
Timer T1 Interrupt Enable for T1B Input cap-
ture edge
C
= 1 µs). A control flag T0EN allows the

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