MC68HC908QY1CP Freescale Semiconductor, MC68HC908QY1CP Datasheet - Page 138

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MC68HC908QY1CP

Manufacturer Part Number
MC68HC908QY1CP
Description
IC MCU 1.5K FLASH 16-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908QY1CP

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

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Development Support
15.2.2.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
BCFE — Break Clear Flag Enable Bit
15.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled,
the break module will remain enabled in wait and stop modes. However, since the internal address bus
does not increment in these modes, a break interrupt will never be triggered.
15.3 Monitor Module (MON)
This subsection describes the monitor module (MON) and the monitor mode entry methods. The monitor
allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with
a host computer. Monitor mode entry can be achieved without use of the higher test voltage, V
long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for
in-circuit programming.
Features include:
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
138
unauthorized users.
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
Normal user-mode pin functionality on most pins
One pin dedicated to serial communication between MCU and host computer
Standard non-return-to-zero (NRZ) communication with host computer
Execution of code in random-access memory (RAM) or FLASH
FLASH memory security feature
FLASH memory programming interface
Use of external 9.8304 MHz oscillator to generate internal frequency of 2.4576 MHz
Simple internal oscillator mode of operation (no external clock or high voltage)
Monitor mode entry without high voltage, V
$FF)
Standard monitor mode entry if high voltage is applied to IRQ
Address: $FE03
Reset:
Read:
Write:
BCFE
Bit 7
R
0
Figure 15-8. Break Flag Control Register (BFCR)
= Reserved
MC68HC908QY/QT Family Data Sheet, Rev. 6
R
6
(1)
R
5
TST
R
4
, if reset vector is blank ($FFFE and $FFFF contain
R
3
R
2
R
1
Freescale Semiconductor
Bit 0
R
TST
, as

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