MC68HC908QY4CP

Manufacturer Part NumberMC68HC908QY4CP
DescriptionIC MCU 4K FLASH W/ADC 16-DIP
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QY4CP datasheet
 

Specifications of MC68HC908QY4CP

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o13Program Memory Size4KB (4K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 4x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case16-DIP (0.300", 7.62mm)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Connectivity-
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MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
MC68HC908QY1
MC68HC908QT1
Data Sheet
M68HC08
Microcontrollers
MC68HC908QY4/D
Rev. 6
03/2010
freescale.com

MC68HC908QY4CP Summary of contents

  • Page 1

    MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet M68HC08 Microcontrollers MC68HC908QY4/D Rev. 6 03/2010 freescale.com ...

  • Page 2

    ...

  • Page 3

    ... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005–2010. All rights reserved. ...

  • Page 4

    ... Chapter 17 Ordering Information and Mechanical Specifications — Added ordering information for DFN package. January, 0.2 4.2 Features — Corrected third bulleted item. 2003 4 Description MC68HC908QY/QT Family Data Sheet, Rev. 6 Page Number(s) N 118 113 92 98 150 99 100 101 103 169 177 185 49 Freescale Semiconductor ...

  • Page 5

    ... FLASH Block Protect Register at address location $FFBE and the Internal January, Oscillator Trim Value at $FFC0. 3.0 2004 Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for clarity. Freescale Semiconductor Description MC68HC908QY/QT Family Data Sheet, Rev. 6 Page Number(s) N/A 20 ...

  • Page 6

    ... Improved RC oscillator wording. — Added note pertaining to non-bonded port pins. — Updated package information. MC68HC908QY/QT Family Data Sheet, Rev. 6 Number(s) Throughout 7.7 Instruction Set Summary: — Clarified bit definitions for 26, 27, 31, 34, 35, 38, Freescale Semiconductor Page 117 127 155 158 54 73 ...

  • Page 7

    ... Chapter 11 Oscillator Module (OSC Chapter 12 Input/Output Ports (PORTS Chapter 13 System Integration Module (SIM 103 Chapter 14 Timer Interface Module (TIM 119 Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 165 Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 8

    ... List of Chapters 8 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 9

    ... ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 Analog-to-Digital Converter (ADC) MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 10

    ... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 Chapter 4 Auto Wakeup Module (AWU) Chapter 5 Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP) MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 11

    ... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.1 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.2 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.6 Keyboard Module During Break Interrupts Freescale Semiconductor Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 12

    ... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.7 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.8 Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.8.1 Oscillator Status Register 11.8.2 Oscillator Trim Register (OSCTRIM Chapter 10 Low-Voltage Inhibit (LVI) Chapter 11 Oscillator Module (OSC) MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 13

    ... Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Freescale Semiconductor Chapter 12 Input/Output Ports (PORTS) Chapter 13 System Integration Module (SIM) MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 14

    ... Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 15.2.2.4 Break Status Register 137 15.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 14 Chapter 14 Timer Interface Module (TIM) Chapter 15 Development Support MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 15

    ... Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.16 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Ordering Information and Mechanical Specifications 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 17.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 17.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Freescale Semiconductor Chapter 16 Electrical Specifications Chapter 17 MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 16

    ... Table of Contents 16 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 17

    ... FLASH security 1. The oscillator frequency is guaranteed to ±5% over temperature and voltage range after trimming security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor 0.4 FLASH Analog-to-Digital Memory Size 1536 bytes ...

  • Page 18

    ... MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in these packages: – 8-pin PDIP – 8-pin SOIC – 8-pin dual flat no lead (DFN) package 18 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 19

    ... MC68HC908QY4. 1.4 Pin Assignments The MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in 8-pin packages and the MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 in 16-pin packages. assignment for these packages. Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev. 6 MCU Block Diagram Figure 1-2 shows the pin ...

  • Page 20

    ... MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH DD SS Figure 1-1. Block Diagram MC68HC908QY/QT Family Data Sheet, Rev. 6 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...

  • Page 21

    ... PTB6 8 9 PTA5/OSC1/KBI5 16-PIN ASSIGNMENT MC68HC908QY1 TSSOP PTA0/TCH0/KBI0 PTA5/OSC1/KB15 4 5 8-PIN ASSIGNMENT MC68HC908QT1 DFN Freescale Semiconductor V SS PTA5/OSC1/AD3/KBI5 PTA0/TCH0/KBI0 PTA4/OSC2/AD2/KBI4 PTA1/TCH1/KBI1 PTA3/RST/KBI3 PTA2/IRQ/KBI2/TCLK MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC V SS PTB0 PTB1 PTA5/OSC1/AD3/KBI5 PTA0/TCH0/KBI0 PTA4/OSC2/AD2/KBI4 PTA1/TCH1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC ...

  • Page 22

    ... Table 1-2. Pin Functions Description 12.1 Introduction). MC68HC908QY/QT Family Data Sheet, Rev. 6 Input/Output Power Power Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input Input Input Input Input/Output Input Input Input/Output Output Output Input Input Input/Output Input Input Input Input/Output Freescale Semiconductor ...

  • Page 23

    ... Pin Name PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 Freescale Semiconductor NOTE Highest-to-Lowest Priority Sequence AD0 → TCH0 → KBI0 → PTA0 AD1 →TCH1 → KBI1 → PTA1 IRQ → KBI2 → TCLK → PTA2 RST → KBI3 → PTA3 OSC2 → AD2 → KBI4 → PTA4 OSC1 → ...

  • Page 24

    ... General Description 24 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 25

    ... Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In register figures in this document, reserved locations are marked with the word Reserved or with the letter R. Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev. 6 Figure 2-1 Figure 2-1 and in ...

  • Page 26

    ... Attempts to execute code from addresses in this range will generate an illegal address reset. (1) (1) Figure 2-1. Memory Map MC68HC908QY/QT Family Data Sheet, Rev. 6 $2E00 UNIMPLEMENTED 51712 BYTES $F7FF $F800 FLASH MEMORY 1536 BYTES $FDFF MC68HC908QT1, MC68HC908QT2, MC68HC908QY1, and MC68HC908QY2 Memory Map Freescale Semiconductor ↓ ↓ ...

  • Page 27

    ... Write: See page 98. Reset: Read: Data Direction Register B $0005 (DDRB) Write: See page 101. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Figure 2-2, contain most of the control, status, and data registers. Bit AWUL R PTA5 PTA4 Unaffected by reset ...

  • Page 28

    ... MC68HC908QY/QT Family Data Sheet, Rev PTAPUE3 PTAPUE2 PTAPUE1 PTBPUE3 PTBPUE2 PTBPUE1 KEYF 0 IMASKK ACKK KBIE3 KBIE2 KBIE1 IRQF 0 IMASK ACK LVI5OR3 SSREC STOP ( PS2 PS1 Bit 11 Bit 10 Bit Reserved U = Unaffected Freescale Semiconductor Bit 0 PTAPUE0 0 PTBPUE0 0 MODEK 0 KBIE0 0 MODE 0 RSTEN (2) 0 COPD 0 PS0 0 Bit 8 0 ...

  • Page 29

    ... Oscillator Status Register $0036 (OSCSTAT) Write: See page 96. Reset: $0037 Unimplemented Read: Oscillator Trim Register Read: (OSCTRIM) Write: $0038 See page 96. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Bit 7 Bit 6 Bit 5 Bit Bit 15 Bit 14 Bit 13 Bit ...

  • Page 30

    ... Writing a 0 clears SBSW. POR PIN COP ILOP BCFE IF5 IF4 IF3 IF14 Unimplemented MC68HC908QY/QT Family Data Sheet, Rev CH3 CH2 CH1 Bit 3 Bit 2 Bit SBSW See note 1 0 ILAD MODRST LVI IF1 Reserved U = Unaffected Freescale Semiconductor Bit 0 CH0 1 Bit BDCOP IF15 ...

  • Page 31

    ... Write: VDD = 5.0 V) Reset: $FFC1 Read: Internal Oscillator Trim (Factory Programmed, Write: VDD = 3.0 V) Reset: Read: COP Control Register $FFFF (COPCTL) Write: See page 59. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Bit 15 Bit 14 Bit 13 Bit Bit 7 ...

  • Page 32

    ... Not used $FFFA IRQ vector (high) IF1 $FFFB IRQ vector (low) $FFFC SWI vector (high) — $FFFD SWI vector (low) $FFFE Reset vector (high) — $FFFF Reset vector (low) NOTE NOTE NOTE MC68HC908QY/QT Family Data Sheet, Rev. 6 Vector Freescale Semiconductor ...

  • Page 33

    ... MASS — Mass Erase Control Bit This read/write bit configures the memory for mass erase operation Mass erase operation selected 0 = Mass erase operation unselected 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor NOTE ...

  • Page 34

    ... Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. 34 NOTE CAUTION MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 35

    ... Set the HVEN bit. (minimum 5 μs). 6. Wait for a time, t PGS 7. Write data to the FLASH address being programmed 1. When in monitor mode, with security sequence failed (see instead of any FLASH address. Freescale Semiconductor (1) within the FLASH memory address range. NOTE NOTE CAUTION NOTE (2) ...

  • Page 36

    ... PGM bit, must not exceed the maximum programming time NOTE NOTE maximum, see PROG NOTE Register. Once the FLBPR is programmed with a value other than , present on the IRQ pin. This voltage also TST maximum. PROG MC68HC908QY/QT Family Data Sheet, Rev. 6 16.16 Freescale Semiconductor ...

  • Page 37

    ... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...

  • Page 38

    ... FLBPR, internal oscillator trim values, and vectors are protected The entire FLASH memory is not protected. MC68HC908QY/QT Family Data Sheet, Rev Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...

  • Page 39

    ... FLASH, or the operation will discontinue and the FLASH will be on standby mode Standby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. Freescale Semiconductor NOTE MC68HC908QY/QT Family Data Sheet, Rev. 6 FLASH Memory (FLASH) ...

  • Page 40

    ... Memory 40 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 41

    ... I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return the corresponding DDR bit the DDR bit the value in the port data latch is read. Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 42

    ... BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH MC68HC908QY/QT Family Data Sheet, Rev. 6 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...

  • Page 43

    ... INTERNAL DATA BUS READ DDRA WRITE DDRA WRITE PTA READ PTA CONVERSION COMPLETE INTERRUPT LOGIC AIEN COCO BUS CLOCK Freescale Semiconductor DDRAx RESET PTAx ADC DATA REGISTER ADC VOLTAGE IN ADCVIN ADC ADC CLOCK CLOCK GENERATOR ADIV[2:0] Figure 3-2. ADC Block Diagram MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 44

    ... ADC by setting the CH[4:0] bits in ADSCR to 1s before executing the WAIT instruction the ADC converts the signal to $FF (full scale). If the input DD NOTE 16 ADC Clock Cycles ADC Clock Frequency MC68HC908QY/QT Family Data Sheet, Rev. 6 and V are a straight-line DD SS and $00 if less than Freescale Semiconductor ...

  • Page 45

    ... In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It always reads Conversion completed (AIEN = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) The write function of the COCO bit is reserved. When writing to the ADSCR register, always have the COCO bit position. Freescale Semiconductor AIEN ...

  • Page 46

    ... CH1 CH0 Channel ADC0 ADC1 ADC2 ADC3 — ↓ ↓ ↓ — — — — — — — MC68HC908QY/QT Family Data Sheet, Rev. 6 Input Select PTA0 PTA1 PTA4 PTA5 (1) Unused Reserved Unused (2) V DDA (2) V SSA ADC power off Freescale Semiconductor ...

  • Page 47

    ... ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 should be set between f ADIC(MIN) entire conversion time (maximum = 17 ADC clock cycles). ADIV2 don’t care Freescale Semiconductor AD6 AD5 AD4 AD3 Indeterminate after reset = Unimplemented Figure 3-4. ADC Data Register (ADR) 6 ...

  • Page 48

    ... Analog-to-Digital Converter (ADC) 48 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 49

    ... COP feature is idle (no MCU clock available) in stop mode. The typical values of the periodic wakeup request are (at room temperature): • COPRS = 0: 650 875 • COPRS = Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev. 6 Figure 4 block diagram of the Figure 4-1. 49 ...

  • Page 50

    ... AUTOWUGEN DIV 2 SHORT DIV 2 OVERFLOW CLK RST RESET ACKK RESET ISTOP AWUIE MC68HC908QY/QT Family Data Sheet, Rev PTA READ, BIT 6 D AWUL Q AWUIREQ KBI INTERRUPT LOGIC (SEE Figure 9-2. Keyboard Interrupt Block Diagram) Figure 4-1) has no effect on AWUL Freescale Semiconductor ...

  • Page 51

    ... Acknowledges keyboard/auto wakeup interrupt requests • Masks keyboard/auto wakeup interrupt requests Address: $001A Bit 7 Read: 0 Write: Reset: 0 Figure 4-3. Keyboard Status and Control Register (KBSCR) Freescale Semiconductor AWUL PTA5 PTA4 PTA3 0 Unaffected by reset Figure 4-2. Port A Data Register (PTA) NOTE 12 ...

  • Page 52

    ... KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Register. 52 NOTE 9.7.1 Keyboard Status and Control AWUIE KBIE5 KBIE4 KBIE3 Unimplemented NOTE 9.7.2 Keyboard Interrupt Enable MC68HC908QY/QT Family Data Sheet, Rev. 6 Register Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...

  • Page 53

    ... The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-1 Address: $001E Bit 7 Read: IRQPUD Write: Reset: 0 POR Reserved Figure 5-1. Configuration Register 2 (CONFIG2) Freescale Semiconductor NOTE and Figure 5- IRQEN R OSCOPT1 OSCOPT0 ...

  • Page 54

    ... LVI disabled during stop mode LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module LVI module resets disabled 0 = LVI module resets enabled 54 DD NOTE LVIRSTD LVIPWRD LVI5OR3 MC68HC908QY/QT Family Data Sheet, Rev Bit 0 SSREC STOP COPD Freescale Semiconductor ...

  • Page 55

    ... STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module COP module disabled 0 = COP module enabled Freescale Semiconductor for the LVI’s voltage trip points for each of the modes. DD NOTE NOTE MC68HC908QY/QT Family Data Sheet, Rev. 6 ...

  • Page 56

    ... Configuration Register (CONFIG) 56 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 57

    ... COPCTL WRITE COPEN (FROM SIM) COP DISABLE (COPD FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) Freescale Semiconductor 12-BIT SIM COUNTER COP CLOCK 6-BIT COP COUNTER CLEAR COP COUNTER Figure 6-1. COP Block Diagram MC68HC908QY/QT Family Data Sheet, Rev. 6 ...

  • Page 58

    ... The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register 58 NOTE NOTE Figure 6.4 COP Control (CONFIG). MC68HC908QY/QT Family Data Sheet, Rev. 6 13.8.1 SIM Reset Status Register. 6-1. Register) clears the COP Freescale Semiconductor ...

  • Page 59

    ... COP timeout period after entering or exiting stop mode. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). Freescale Semiconductor (CONFIG ...

  • Page 60

    ... Computer Operating Properly (COP) 60 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 61

    ... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 62

    ... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H:X) MC68HC908QY/QT Family Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...

  • Page 63

    ... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...

  • Page 64

    ... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908QY/QT Family Data Sheet, Rev Bit Freescale Semiconductor ...

  • Page 65

    ... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev. 6 Arithmetic/Logic Unit (ALU) ...

  • Page 66

    ... REL – – – – – – REL 90 ⊕ – – – – – – REL 92 – – – – – – REL 28 – – – – – – REL 29 – – – – – – REL 22 Freescale Semiconductor ...

  • Page 67

    ... CBEQA #opr,rel CBEQX #opr,rel CBEQ opr,X+,rel Compare and Branch if Equal CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ⊕ ...

  • Page 68

    ... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...

  • Page 69

    ... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...

  • Page 70

    ... DIR 35 dd – – 0 – – – INH 8E DIR BF dd EXT IX2 – – – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...

  • Page 71

    ... M Memory location N Negative bit 7.8 Opcode Map See Table 7-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...

  • Page 72

    Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

  • Page 73

    ... Reset — A reset automatically clears the IRQ latch. The external interrupt pin is falling-edge-triggered out of reset and is software-configurable to be either falling-edge or falling-edge and low-level triggered. The MODE bit in INTSCR controls the triggering sensitivity of the IRQ pin. Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 74

    ... MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH NOTE MC68HC908QY/QT Family Data Sheet, Rev. 6 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...

  • Page 75

    ... The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by IMASK, which makes it useful in applications where polling is preferred. When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interrupt routine. Freescale Semiconductor V DD CLR ...

  • Page 76

    ... When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pullup resistor connected to the IRQ pin; this can be disabled by setting DD the IRQPUD bit in the CONFIG2 register ($001E). 76 Chapter 13 System Integration Module (SIM). NOTE MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 77

    ... IRQ interrupt request disabled 0 = IRQ interrupt request enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling edges only Freescale Semiconductor (CONFIG ...

  • Page 78

    ... External Interrupt (IRQ) 78 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 79

    ... If the keyboard interrupt is falling edge and low-level sensitive, an interrupt request is present as long as any keyboard interrupt input is low. Freescale Semiconductor Register). A logic 0 applied to an enabled keyboard interrupt pin MC68HC908QY/QT Family Data Sheet, Rev. 6 Figure 9-2. ...

  • Page 80

    ... BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH MC68HC908QY/QT Family Data Sheet, Rev. 6 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...

  • Page 81

    ... The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. Freescale Semiconductor V DD CLR ...

  • Page 82

    ... To allow software to clear the keyboard interrupt latch during a break interrupt, write the BCFE bit latch is cleared during the break state, it remains cleared when the MCU exits the break state. 82 NOTE MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 83

    ... Keyboard interrupt requests not masked MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A and auto wakeup. Reset clears MODEK Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only Freescale Semiconductor ...

  • Page 84

    ... KBIx pin not enabled as keyboard interrupt pin AWUIE bit is not used in conjunction with the keyboard interrupt feature. To see a description of this bit, see AWUIE KBIE5 KBIE4 KBIE3 NOTE Chapter 4 Auto Wakeup Module MC68HC908QY/QT Family Data Sheet, Rev Bit 0 KBIE2 KBIE1 KBIE0 (AWU). Freescale Semiconductor ...

  • Page 85

    ... The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V reset disable bit, LVIRSTD, enables the LVI module to generate a reset when V Freescale Semiconductor voltage falls below the LVI trip falling voltage ...

  • Page 86

    ... MC68HC908QY/QT Family Data Sheet, Rev configured TRIPF , to be configured for 3-V TRIPF and for 5-V mode. TRIPR rises above a voltage which TRIPR for the reset recovery level, software can monitor greater than TRIPF TRIPR 16.9 3-V DC Electrical Freescale Semiconductor 16.9 3-V by polling ...

  • Page 87

    ... When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. Freescale Semiconductor voltage was detected below the V DD ...

  • Page 88

    ... Low-Voltage Inhibit (LVI) 88 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 89

    ... External crystal: A built-in oscillator module (XTAL oscillator) that requires an external crystal or ceramic-resonator. 11.3 Functional Description The oscillator contains these major subsystems: • Internal oscillator circuit • Internal or external clock switch control • External clock circuit • External crystal circuit • External RC clock circuit Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 90

    ... MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH Chapter 12 Input/Output Ports (PORTS) MC68HC908QY/QT Family Data Sheet, Rev. 6 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...

  • Page 91

    ... BUSCLKX4 and also divided by two to create BUSCLKX2. In this configuration, the OSC2 pin cannot output BUSCLKX4.So the OSC2EN bit in the port A pullup enable register will be clear to enable PTA4 I/O functions on the pin Freescale Semiconductor NOTE MC68HC908QY/QT Family Data Sheet, Rev. 6 ...

  • Page 92

    ... Refer to manufacturer’s S data. See Chapter 16 Electrical Specifications Figure 11-2. XTAL Oscillator External Connections 92 NOTE ) is included in the diagram to follow strict Pierce S TO SIM BUSCLKX4 BUSCLKX2 XTALCLK OSC2 R ( for component value recommendations. MC68HC908QY/QT Family Data Sheet, Rev SIM ÷ 2 Freescale Semiconductor ...

  • Page 93

    ... Crystal Amplifier Input Pin (OSC1) The OSC1 pin is either an input to the crystal oscillator amplifier, an input to the RC oscillator circuit external clock source. For the internal oscillator configuration, the OSC1 pin can assume other functions according to Function Priority in Shared Pins. Freescale Semiconductor Figure INTCLK 0 1 EXTERNAL RC ...

  • Page 94

    ... Controlled by OSC2EN bit in PTAPUE register OSC2EN = 0: PTA4 I/O OSC2EN = 1: BUSCLKX4 output Figure 11-2 shows only the logical relation of XTALCLK to OSC1 shows only the logical relation of RCCLK to OSC1 and may not MC68HC908QY/QT Family Data Sheet, Rev and comes XCLK 11.3.1.1 Internal Freescale Semiconductor ...

  • Page 95

    ... OSCOPT bits are used to select the oscillator clock source. OSCOPT1 11.8 Input/Output (I/O) Registers The oscillator module contains these two registers: 1. Oscillator status register (OSCSTAT) 2. Oscillator trim register (OSCTRIM) Freescale Semiconductor . Table 11-2. Oscillator Modes OSCOPT0 Oscillator Modes 0 Internal oscillator 1 External oscillator 0 ...

  • Page 96

    ... Applications using the internal oscillator should copy the internal oscillator trim value at location $FFC0 or $FFC1 into this register to trim the clock source Unimplemented TRIM6 TRIM5 TRIM4 TRIM3 MC68HC908QY/QT Family Data Sheet, Rev Bit 0 ECGST R ECGON Bit 0 TRIM2 TRIM1 TRIM0 Freescale Semiconductor ...

  • Page 97

    ... PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin. Freescale Semiconductor NOTE (KBI)). Each port A pin also has a software configurable pullup NOTE MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 98

    ... Figure 12-1. Port A Data Register (PTA) Chapter 4 Auto Wakeup Module DDRA5 DDRA4 DDRA3 Reserved = Unimplemented NOTE MC68HC908QY/QT Family Data Sheet, Rev Bit 0 PTA2 PTA3 PTA1 PTA0 KBI3 KBI2 KBI1 KBI0 = Unimplemented (AWU)). There is no PTA6 Chapter 9 Keyboard Interrupt Module 2 1 Bit 0 0 DDRA1 DDRA0 Freescale Semiconductor ...

  • Page 99

    ... This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is selected. This bit has no effect for the XTAL or external oscillator options OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4 OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions Freescale Semiconductor DDRAx RESET PTAx Figure 12-3 ...

  • Page 100

    ... DDRA5–DDRA0 PTB6 PTB5 PTB4 PTB3 Unaffected by reset Figure 12-5. Port B Data Register (PTB) MC68HC908QY/QT Family Data Sheet, Rev. 6 Accesses to PTA Read Write Pin PTA5–PTA0 Pin PTA5–PTA0 PTA5–PTA0 PTA5–PTA0 2 1 Bit 0 PTB2 PTB1 PTB0 Freescale Semiconductor (3) (3) (5) ...

  • Page 101

    ... The data latch can always be written, regardless of the state of its data direction bit. Table 12-2 DDRB PTB Bit Bit ( don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect the input. Freescale Semiconductor DDRB6 DDRB5 DDRB4 DDRB3 NOTE DDRBx ...

  • Page 102

    ... I/O Pin Mode Read/Write (2) Input, V DDRB7–DDRB0 DD (4) DDRB7–DDRB0 Input, Hi-Z Output DDRB7–DDRB0 MC68HC908QY/QT Family Data Sheet, Rev Bit 0 PTBPUE2 PTBPUE2 PTBPUE0 Accesses to PTB Read Write Pin PTB7–PTB0 Pin PTB7–PTB0 PTB7–PTB0 PTB7–PTB0 Freescale Semiconductor (3) (3) ...

  • Page 103

    ... Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal Freescale Semiconductor Figure Table 13-1. Signal Name Conventions Description MC68HC908QY/QT Family Data Sheet, Rev. 6 13-1. The SIM is a system state controller 103 ...

  • Page 104

    ... BUSCLKX2 (FROM OSCILLATOR) INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) FORCED MON MODE ENTRY (FROM MENRST MODULE) INTERRUPT SOURCES CPU INTERFACE (CONFIG). Figure 13-2. Freescale Semiconductor ...

  • Page 105

    ... IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see the resets sets a corresponding bit in the SIM reset status register (SRSR). See Freescale Semiconductor FROM BUSCLKX4 SIM COUNTER ...

  • Page 106

    ... The RST pin function is only available Figure 13-3. External Reset Timing NOTE RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 13-4. Internal Reset Timing MC68HC908QY/QT Family Data Sheet, Rev. 6 VECT H VECT L Figure 13-4. VECTOR HIGH Freescale Semiconductor ...

  • Page 107

    ... See Figure 13-6. OSC1 PORRST 4096 CYCLES BUSCLKX4 BUSCLKX2 RST ADDRESS BUS Freescale Semiconductor ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET POR LVI Figure 13-5. Sources of Internal Reset Table 13-2. Reset Recovery Timing Actual Number of Cycles POR/LVI 4163 (4096 + ...

  • Page 108

    ... PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine. 108 Figure 2-1. Memory Map voltage falls to the LVI trip voltage V DD rises above V DD MC68HC908QY/QT Family Data Sheet, Rev. 6 for memory ranges. . The LVI TRIPF . Sixty-four BUSCLKX4 TRIPR Freescale Semiconductor ...

  • Page 109

    ... At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. interrupt entry timing. Figure 13-9 Freescale Semiconductor 13.7.2 Stop Mode 13.4.2 Active Resets from Internal Sources shows interrupt recovery timing. ...

  • Page 110

    ... I BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? NO Figure 13-7. Interrupt Processing MC68HC908QY/QT Family Data Sheet, Rev. 6 STACK CPU REGISTERS SET I BIT UNSTACK CPU REGISTERS EXECUTE INSTRUCTION Freescale Semiconductor ...

  • Page 111

    ... To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. Freescale Semiconductor SP – – – – ...

  • Page 112

    ... INT Vector (1) Register Address Flag — $FFFE–$FFFF — $FFFC–$FFFD IF1 $FFFA–$FFFB IF3 $FFF6–$FFF7 IF4 $FFF4–$FFF5 IF5 $FFF2–$FFF3 IF14 $FFE0–$FFE1 IF15 $FFDE–$FFDF Freescale Semiconductor ...

  • Page 113

    ... Read: 0 Write: R Reset Reserved Figure 13-13. Interrupt Status Register 3 (INT3) IF15 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Bit 1–7 — Always read 0 Freescale Semiconductor IF5 IF4 IF3 ...

  • Page 114

    ... NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. 114 Support.) The SIM puts the CPU into the break WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 13-14. Wait Mode Entry Timing MC68HC908QY/QT Family Data Sheet, Rev. 6 Figure 13-14 shows SAME SAME SAME Freescale Semiconductor ...

  • Page 115

    ... This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time by clearing the SSREC bit. Freescale Semiconductor show the timing for wait recovery. $6E0B $6E0C ...

  • Page 116

    ... STOP + 2 Table 13-4 shows the mapping of these registers. Table 13-4. SIM Registers Register BSR SRSR BFCR MC68HC908QY/QT Family Data Sheet, Rev. 6 shows stop mode entry timing and SAME SAME SAME SP SP – – – 3 Access Mode User User User Freescale Semiconductor ...

  • Page 117

    ... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ ≠ V TST 0 = POR or read of SRSR LVI — Low Voltage Inhibit Reset Bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR Freescale Semiconductor PIN COP ...

  • Page 118

    ... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break 118 MC68HC908QY/QT Family Data Sheet, Rev Bit Freescale Semiconductor ...

  • Page 119

    ... The TIM shares two input/output (I/O) pins with two port A I/O pins. The full names of the TIM I/O pins are listed in Table 14-1. The generic pin name appear in the text that follows. TIM Generic Pin Names: Full TIM Pin Names: Freescale Semiconductor Table 14-1. Pin Name Conventions TCH0 TCH1 PTA0/TCH0 PTA1/TCH1 MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 120

    ... BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH MC68HC908QY/QT Family Data Sheet, Rev. 6 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...

  • Page 121

    ... BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH Freescale Semiconductor PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A CH1F MS1A Figure 14-2. TIM Block Diagram MC68HC908QY/QT Family Data Sheet, Rev ...

  • Page 122

    ... The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers ( that 122 MC68HC908QY/QT Family Data Sheet, Rev. 6 14.4.3 Freescale Semiconductor ...

  • Page 123

    ... PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. OVERFLOW POLARITY = 1 TCHx (ELSxA = 0) POLARITY = 0 TCHx (ELSxA = 1) Figure 14-3. PWM Period and Pulse Width Freescale Semiconductor NOTE 14.9.1 TIM Status and Control OVERFLOW PERIOD PULSE WIDTH OUTPUT COMPARE MC68HC908QY/QT Family Data Sheet, Rev. 6 Functional Description Register ...

  • Page 124

    ... User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 124 NOTE NOTE MC68HC908QY/QT Family Data Sheet, Rev. 6 14.4.4 Pulse Width Freescale Semiconductor ...

  • Page 125

    ... Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE =1. CHxF and CHxIE are in the TIM channel x status and control register. Freescale Semiconductor NOTE Registers. MC68HC908QY/QT Family Data Sheet, Rev. 6 ...

  • Page 126

    ... TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0 and TSC1) • TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L) 126 13.8.2 Break Flag Control Register. Register.) When the PTA2/TCLK pin is the TIM clock input, MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 127

    ... TSTOP bit is cleared. When using TSTOP to stop the timer counter, see if any timer flags are set timer flag is set, it must be cleared by clearing TSTOP, then clearing the flag, then setting TSTOP again. Freescale Semiconductor ...

  • Page 128

    ... Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ PTA2/TCLK NOTE Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit MC68HC908QY/QT Family Data Sheet, Rev Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...

  • Page 129

    ... Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger • Selects output toggling on TIM overflow • Selects 0% and 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation Freescale Semiconductor Bit 14 Bit 13 Bit 12 Bit 11 ...

  • Page 130

    ... When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See 1 = Unbuffered output compare/PWM operation 0 = Input capture operation 130 CH0IE MS0B MS0A ELS0B CH1IE MS1A ELS1B Registers (TSC0:TSC1) Table 14-3. MC68HC908QY/QT Family Data Sheet, Rev Bit 0 ELS0A TOV0 CH0MAX Bit 0 ELS1A TOV1 CH1MAX Freescale Semiconductor ...

  • Page 131

    ... Reset clears the TOVx bit Channel x pin toggles on TIM counter overflow Channel x pin does not toggle on TIM counter overflow. When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. Freescale Semiconductor NOTE ELSxA Mode 0 Pin under port control ...

  • Page 132

    ... Bit 13 Bit 12 Bit 11 Indeterminate after reset Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset MC68HC908QY/QT Family Data Sheet, Rev. 6 OVERFLOW OVERFLOW OUTPUT COMPARE 2 1 Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit 0 Freescale Semiconductor ...

  • Page 133

    ... When a CPU generated address matches the contents of the break address registers, the break interrupt is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. Figure 15-2 shows the structure of the break module. Freescale Semiconductor MC68HC908QY/QT Family Data Sheet, Rev. 6 133 ...

  • Page 134

    ... COMPARATOR BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] MC68HC908QY/QT Family Data Sheet, Rev. 6 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM CONTROL BKPT (TO SIM) Freescale Semiconductor ...

  • Page 135

    ... Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) Freescale Semiconductor CAUTION 13.8.2 Break Flag Control Register MC68HC908QY/QT Family Data Sheet, Rev. 6 Break Module (BRK) and the Break Interrupts subsection 135 ...

  • Page 136

    ... Figure 15-4. Break Address Register High (BRKH) Address: $FE0A Bit 7 Read: Bit 7 Write: Reset: 0 Figure 15-5. Break Address Register Low (BRKL) 136 BRKA Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit MC68HC908QY/QT Family Data Sheet, Rev Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...

  • Page 137

    ... SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt Freescale Semiconductor ...

  • Page 138

    ... Standard monitor mode entry if high voltage is applied to IRQ 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 138 ( reset vector is blank ($FFFE and $FFFF contain TST MC68HC908QY/QT Family Data Sheet, Rev Bit TST Freescale Semiconductor ...

  • Page 139

    ... PTA0 = 1, FROM Table 15-1 RESET VECTOR BLANK? YES FORCED MONITOR MODE DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) Figure 15-9. Simplified Monitor Mode Entry Flowchart Freescale Semiconductor POR RESET NO YES IRQ = V ? TST NO NORMAL USER MODE HOST SENDS 8 SECURITY BYTES YES IS RESET POR? ...

  • Page 140

    ... MC68HC908QY/QT Family Data Sheet, Rev RST (PTA3) OSC1 (PTA5) PTA1 IRQ (PTA2) PTA4 PTA0 Value not critical N.C. RST (PTA3 OSC1 (PTA5) * PTA1 IRQ (PTA2) PTA4 PTA0 Value not critical Freescale Semiconductor V DD 0.1 μ kΩ kΩ 0.1 μF N.C. N.C. ...

  • Page 141

    ... If $FFFE and $FFFF contain $FF (erased state): – The external clock is 9.8304 MHz – IRQ = V (this can be implemented through the internal IRQ pullup) DD • If $FFFE and $FFFF contain $FF (erased state): – IRQ = V (internal oscillator is selected, no external clock required) SS Freescale Semiconductor μF 1 μ kΩ kΩ + 74HC125 ...

  • Page 142

    ... MHz MHz clock at OSC1. 9.8304 2.4576 Provide external 9600 MHz MHz clock at OSC1. 3.2 MHz Internal clock X 9600 (Trimmed) is active OSC1 — — [13] 15.3.2 Security). After the TST ) then the chip will still be operating in lowered, the BIH and TST Freescale Semiconductor is ...

  • Page 143

    ... Pulling RST (when RST pin available) low will not exit monitor mode in this situation. Table 15-2 summarizes the differences between user mode and monitor mode regarding vectors. Freescale Semiconductor on IRQ, then the COP is disabled as long as V TST NOTE , the MCU will come out of reset in user mode ...

  • Page 144

    ... Figure 15-13. Monitor Data Format MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO Figure 15-14. Break Transaction Table 15-1. MC68HC908QY/QT Family Data Sheet, Rev. 6 SWI SWI Vector High Vector Low $FFFC $FFFD $FEFC $FEFD NEXT START STOP BIT 7 BIT BIT Freescale Semiconductor ...

  • Page 145

    ... A brief description of each monitor mode command is given in Table 15-3. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode $4A SENT TO MONITOR READ READ ECHO Freescale Semiconductor NOTE ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte ...

  • Page 146

    ... Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH LOW HIGH LOW Command Sequence FROM HOST IREAD IREAD DATA Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO MC68HC908QY/QT Family Data Sheet, Rev. 6 DATA DATA DATA RETURN Freescale Semiconductor ...

  • Page 147

    ... CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value The high and low bytes of the program counter are at addresses and Figure 15-17. Stack Pointer at Monitor Mode Entry Freescale Semiconductor Command Sequence SP READSP ...

  • Page 148

    ... Notes Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. Figure 15-18. Monitor Mode Entry Timing 148 NOTE Figure 15-18. NOTE 4096 + 32 CGMXCLK CYCLES (MINIMUM) FROM MCU MC68HC908QY/QT Family Data Sheet, Rev Freescale Semiconductor ...

  • Page 149

    ... For proper operation recommended that V ≤ range unused inputs are connected to an appropriate logic voltage level (for example, either V Freescale Semiconductor NOTE and (1) Symbol and PTA0— ...

  • Page 150

    ... MC68HC908QY/QT Family Data Sheet, Rev. 6 Temp. Value Unit Code – +125 M – +105 •C V – +85 C 2.7 to 5.5 V — Value Unit 105 142 173 •C 133 User determined K/(T + 273•C) I 273• W/• θ θ • 150 •C With this value and Freescale Semiconductor ...

  • Page 151

    ... Typical values reflect average measurements at midpoint of voltage range, 25•C only. 3. Maximum is highest voltage that POR is guaranteed minimum V is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum reached measured 5 Freescale Semiconductor Symbol OHT OLT ...

  • Page 152

    ... Figure 16-1. Typical 5-Volt Output High Voltage 2.0 1.5 1.0 0.5 0.0 0 Figure 16-2. Typical 5-Volt Output Low Voltage 152 -5 -10 -15 -20 -25 IOH (mA) versus Output High Current (25• IOL (mA) versus Output Low Current (25•C) MC68HC908QY/QT Family Data Sheet, Rev PTA 5V PTB -30 -35 5V PTA 5V PTB 30 35 Freescale Semiconductor ...

  • Page 153

    ... RST input pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period 4.5 to 5.5 Vdc Vdc noted. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t RST IRQ Freescale Semiconductor (1) Symbol timing shown with respect to 20 ...

  • Page 154

    ... C — — — — See Figure 16-4 — 20 — — 10 — — 0 — 25° Freescale Semiconductor Unit MHz % MHz MHz MHz pF — — MΩ — kΩ ...

  • Page 155

    ... Typical values reflect average measurements at midpoint of voltage range, 25•C only. 3. Maximum is highest voltage that POR is guaranteed minimum V is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum reached are measured 3 Freescale Semiconductor Symbol OHT OLT V 0 ...

  • Page 156

    ... Figure 16-5. Typical 3-Volt Output High Voltage 1.5 1.0 0.5 0.0 0 Figure 16-6. Typical 3-Volt Output Low Voltage 156 -5 -10 -15 IOH (mA) versus Output High Current (25• IOL (mA) versus Output Low Current (25•C) MC68HC908QY/QT Family Data Sheet, Rev PTA 3V PTB -20 3V PTA 3V PTB 20 Freescale Semiconductor ...

  • Page 157

    ... RST input pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period 2.7 to 3.3 Vdc Vdc noted. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t RST IRQ Freescale Semiconductor (1) Symbol timing shown with respect to 20 ...

  • Page 158

    ... C — — — — See Figure 16-8 — 10 — — 5 — — 0 — 25° Freescale Semiconductor Unit MHz % MHz MHz MHz pF — — MΩ — kΩ ...

  • Page 159

    ... ADC off, all other modules enabled. All pins configured as inputs and DD tied to 0.2 V from rail. 5. Stop I measured with all pins tied to 0 less from rail loads. On the 8-pin versions, port B is configured as DD inputs with pullups enabled. Freescale Semiconductor Bus Voltage Frequency (MHz) 5.0 3.2 3 ...

  • Page 160

    ... Bus Frequency (25• Bus Frequency (MHz) versus Bus Frequency (25•C) MC68HC908QY/QT Family Data Sheet, Rev. 6 Crystal w/o ADC Crystal w/ ADC Internal Osc w/o ADC Internal Osc w/ ADC 7 Crystal w/o ADC Crystal w/ ADC Internal Osc w/o ADC Internal Osc w/ ADC 5 Freescale Semiconductor ...

  • Page 161

    ... Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling. 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current. Freescale Semiconductor Symbol Min Max 2 ...

  • Page 162

    ... FALLING EDGE INPUT CAPTURE BOTH EDGES TCLK 162 t TLTL TLTL t TLTL TCH t TCL Figure 16-11. Timer Input Timing MC68HC908QY/QT Family Data Sheet, Rev. 6 Symbol Min Max — TH (1) — Note TLTL — TCL TCH cyc . cyc Freescale Semiconductor Unit t cyc t cyc ns ...

  • Page 163

    ... Endurance, please refer to Engineering Bulletin EB619. 5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25•C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618. Freescale Semiconductor Symbol V RDR — ...

  • Page 164

    ... Electrical Specifications 164 MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor ...

  • Page 165

    ... P = Plastic dual in-line package (PDIP Small outline integrated circuit package (SOIC Thin shrink small outline package (TSSOP Dual flat no lead (DFN) 17.3 Package Dimensions Refer to the following pages for detailed package dimensions. Freescale Semiconductor Table 17-1. MC Order Numbers ADC FLASH Memory — 1536 bytes ...

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    ... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...