MC68HC908QY4CDW Freescale Semiconductor, MC68HC908QY4CDW Datasheet - Page 101

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MC68HC908QY4CDW

Manufacturer Part Number
MC68HC908QY4CDW
Description
IC MCU 4K FLASH W/ADC 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908QY4CDW

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-

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12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
DDRB[7:0] — Data Direction Register B Bits
When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading
address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit.
Freescale Semiconductor
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Address: $0005
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
DDRB
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
port B I/O logic.
Reset:
Read:
Write:
Bit
0
1
READ DDRB ($0005)
WRITE DDRB ($0005)
WRITE PTB ($0001)
READ PTB ($0001)
DDRB7
Bit 7
PTB
X
0
Bit
X
(1)
Figure 12-6. Data Direction Register B (DDRB)
Table 12-2
DDRB6
Input, Hi-Z
MC68HC908QY/QT Family Data Sheet, Rev. 6
6
0
I/O Pin
Output
RESET
Mode
Table 12-2. Port B Pin Functions
Figure 12-7. Port B I/O Circuit
DDRB5
(2)
summarizes the operation of the port B pins.
5
0
Accesses to DDRB
DDRB7–DDRB0
DDRB7–DDRB0
DDRBx
DDRB4
NOTE
PTBx
Read/Write
4
0
DDRB3
3
0
Figure 12-7
DDRB2
Read
2
0
Pin
Pin
PTBPUEx
Accesses to PTB
DDRB1
PTB7–PTB0
PTB7–PTB0
1
0
shows the
Write
30 k
DDRB0
Bit 0
PTBx
0
(3)
Port B
101

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