C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet
C8051F321R
Specifications of C8051F321R
Related parts for C8051F321R
C8051F321R Summary of contents
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ANALOG PERIPHERALS - 10-Bit ADC • 200 ksps • External Single-Ended or Differential Inputs • VREF from External Pin, Internal Reference, or VDD • Built-in Temperature Sensor • External Conversion Start Input - ...
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C8051F320/1 2 Notes Rev. 1.1 ...
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TABLE OF CONTENTS 1. SYSTEM OVERVIEW .........................................................................................................17 1.1. CIP-51™ Microcontroller Core ......................................................................................20 1.1.1. Fully 8051 Compatible ..........................................................................................20 1.1.2. Improved Throughput ............................................................................................20 1.1.3. Additional Features................................................................................................21 1.2. On-Chip Memory ............................................................................................................22 1.3. Universal Serial Bus Controller.......................................................................................23 1.4. Voltage Regulator............................................................................................................23 1.5. On-Chip Debug Circuitry ...
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C8051F320/1 9.2.7. Register Descriptions .............................................................................................84 9.3. Interrupt Handler .............................................................................................................87 9.3.1. MCU Interrupt Sources and Vectors .....................................................................87 9.3.2. External Interrupts .................................................................................................88 9.3.3. Interrupt Priorities..................................................................................................88 9.3.4. Interrupt Latency....................................................................................................88 9.3.5. Interrupt Register Descriptions ..............................................................................90 9.4. Power Management Modes .............................................................................................96 9.4.1. Idle Mode ...............................................................................................................96 ...
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I/O Initialization.....................................................................................................131 14.3.General Purpose Port I/O...............................................................................................134 15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ....................................................143 15.1.Endpoint Addressing .....................................................................................................144 15.2.USB Transceiver ...........................................................................................................144 15.3. USB Register Access.....................................................................................................146 15.4.USB Clock Configuration .............................................................................................150 15.5. FIFO Management.........................................................................................................151 15.5.1. FIFO Split Mode ..................................................................................................151 15.5.2. FIFO Double Buffering ...
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C8051F320/1 17.1. Enhanced Baud Rate Generation...................................................................................194 17.2.Operational Modes ........................................................................................................195 17.2.1. 8-Bit UART .........................................................................................................195 17.2.2. 9-Bit UART .........................................................................................................196 17.3.Multiprocessor Communications...................................................................................197 18. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) .........................................203 18.1. Signal Descriptions........................................................................................................204 18.1.1. Master Out, Slave In (MOSI) ..............................................................................204 18.1.2. Master In, Slave ...
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Pin Sharing...............................................................................................................255 C8051F320/1 Rev. 1.1 7 ...
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C8051F320/1 8 Notes Rev. 1.1 ...
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LIST OF FIGURES AND TABLES 1. SYSTEM OVERVIEW ........................................................................................................17 Table 1.1. Product Selection Guide ......................................................................................17 Figure 1.1. C8051F320 Block Diagram.................................................................................18 Figure 1.2. C8051F321 Block Diagram.................................................................................19 Figure 1.3. Comparison of Peak MCU Execution Speeds.....................................................20 Figure 1.4. On-Chip Clock and Reset....................................................................................21 Figure ...
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C8051F320/1 Figure 5.15. ADC Window Compare Example: Right-Justified Single-Ended Data..............52 Figure 5.16. ADC Window Compare Example: Left-Justified Single-Ended Data ................52 Figure 5.17. ADC Window Compare Example: Right-Justified Differential Data.................53 Figure 5.18. ADC Window Compare Example: Left-Justified Differential Data ...................53 Table ...
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Figure 9.14. EIP2: Extended Interrupt Priority 2.....................................................................94 Figure 9.15. IT01CF: INT0/INT1 Configuration Register ......................................................95 Figure 9.16. PCON: Power Control Register ..........................................................................97 10. RESET SOURCES .............................................................................................................99 Figure 10.1. Reset Sources ......................................................................................................99 Figure 10.2. Power-On and VDD Monitor Reset Timing .....................................................100 Figure ...
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C8051F320/1 Figure 14.16. P2MDIN: Port2 Input Mode Register .............................................................139 Figure 14.17. P2MDOUT: Port2 Output Mode Register.......................................................140 Figure 14.18. P2SKIP: Port2 Skip Register...........................................................................140 Figure 14.19. P3: Port3 Register............................................................................................141 Figure 14.20. P3MDIN: Port3 Input Mode Register .............................................................141 Figure 14.21. P3MDOUT: Port3 Output ...
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Table 16.2. Minimum SDA Setup and Hold Times .............................................................181 Figure 16.5. SMB0CF: SMBus Clock/Configuration Register .............................................182 Figure 16.6. SMB0CN: SMBus Control Register .................................................................184 Table 16.3. Sources for Hardware Changes to SMB0CN ....................................................185 Figure 16.7. SMB0DAT: SMBus Data Register ...................................................................186 Figure ...
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C8051F320/1 Figure 19.3. T0 Mode 3 Block Diagram................................................................................220 Figure 19.4. TCON: Timer Control Register.........................................................................221 Figure 19.5. TMOD: Timer Mode Register...........................................................................222 Figure 19.6. CKCON: Clock Control Register......................................................................223 Figure 19.7. TL0: Timer 0 Low Byte ....................................................................................224 Figure 19.8. TL1: Timer 1 Low ...
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Figure 20.16. PCA0CPLn: PCA Capture Module Low Byte ................................................252 Figure 20.17. PCA0CPHn: PCA Capture Module High Byte ...............................................252 21. C2 INTERFACE .................................................................................................................253 Figure 21.1. C2ADD: C2 Address Register ..........................................................................253 Figure 21.2. DEVICEID: C2 Device ID Register .................................................................253 Figure 21.3. REVID: ...
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C8051F320/1 16 Notes Rev. 1.1 ...
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SYSTEM OVERVIEW C8051F320/1 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core ( MIPS) • In-system, full-speed, non-intrusive debug ...
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C8051F320/1 Figure 1.1. C8051F320 Block Diagram 5.0V Voltage Enable REGIN IN Regulator OUT Analog/Digital VDD Power GND C2D Debug HW /RST/C2CK Brown- POR Out XTAL1 XTAL2 External Oscillator Circuit 12MHz Internal x4 2 Oscillator 2 USB Clock Clock 1,2,3,4 Recovery ...
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Figure 1.2. C8051F321 Block Diagram 5.0V Voltage Enable REGIN IN Regulator OUT Analog/Digital VDD Power GND C2D Debug HW /RST/C2CK Brown- POR Out XTAL1 XTAL2 External Oscillator Circuit 12MHz Internal x4 2 Oscillator 2 USB Clock Clock 1,2,3,4 Recovery USB ...
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C8051F320/1 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F320/1 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compat- ible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop ...
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Additional Features The C8051F320/1 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve per- formance and ease of use in end applications. The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as ...
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C8051F320/1 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and ...
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Universal Serial Bus Controller The Universal Serial Bus Controller (USB0 USB 2.0 compliant Full or Low Speed function with integrated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional control endpoint ...
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C8051F320/1 1.5. On-Chip Debug Circuitry The C8051F320/1 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification ...
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Programmable Digital I/O and Crossbar C8051F320 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F321 devices include 21 I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The C8051F320/1 Ports behave like ...
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C8051F320/1 1.8. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programmable capture/com- pare modules. The PCA ...
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Analog to Digital Converter The C8051F320/1 devices include an on-chip 10-bit SAR ADC with a 17-channel differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB. The ...
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C8051F320/1 1.10. Comparators C8051F320/1 devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port ...
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ABSOLUTE MAXIMUM RATINGS Table 2.1. Absolute Maximum Ratings PARAMETER Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or /RST with respect to GND Voltage on VDD with respect to GND Maximum Total current through VDD ...
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C8051F320/1 3. GLOBAL DC ELECTRICAL CHARACTERISTICS Table 3.1. Global DC Electrical Characteristics -40°C to +85°C, 25 MHz System Clock unless otherwise specified. PARAMETER Digital Supply Voltage (Note 1) Digital Supply Current with CPU VDD=3.3V, Clock=24MHz active VDD=3.3V, Clock=1MHz VDD=3.3V, Clock=32kHz ...
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PINOUT AND PACKAGE DEFINITIONS Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name ‘F320 ‘F321 VDD 6 6 GND 3 3 /RST C2CK P3. C2D REGIN 7 7 VBUS ...
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C8051F320/1 Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name ‘F320 ‘F321 P0. CNVSTR P0. VREF P1.6 ...
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Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name Type ‘F320 ‘F321 D I Figure 4.1. LQFP-32 Pinout Diagram (Top View) 1 P0.1 2 P0.0 3 GND VDD 7 ...
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C8051F320/1 Figure 4.2. LQFP-32 Package Diagram PIN 1 IDENTIFIER Table 4.2. LQFP-32 Package Dimensions MIN 0.05 A2 1. ...
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Figure 4.3. MLP-28 Pinout Diagram (Top View) GND P0.1 1 P0.0 2 GND 3 C8051F321 D+ 4 Top View D- 5 VDD 6 REGIN 7 C8051F320 GND 15 Rev. 1.1 P1.1 P1.2 P1.3 P1.4 ...
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C8051F320/1 Figure 4.4. MLP-28 Package Drawing Bottom View DETAIL Side View DETAIL ...
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Figure 4.5. Typical MLP-28 Landing Diagram 0.50 mm 0.20 mm Optional GND Connection L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm C8051F320/1 Top View E2 E Rev. 1.1 0. ...
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C8051F320/1 Figure 4.6. Typical MLP-28 Solder Mask 0.50 mm 0.60 mm 0. 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0. Top View 0.60 mm 0.30 mm 0. ...
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ADC (ADC0) The ADC0 subsystem for the C8051F320/1 consists of two analog multiplexers (referred to collectively as AMUX0) with 17 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track- and-hold and programmable window detector. ...
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C8051F320/1 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: P1.0-P3.0, the on-chip temperature sensor, or the positive power supply (VDD). Any of the following ...
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Temperature Sensor The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (V ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Figure 5.2. Typical Temperature Sensor Transfer Function (mV) ...
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C8051F320/1 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC ...
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Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates ...
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C8051F320/1 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 ...
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Figure 5.5. AMX0P: AMUX0 Positive Channel Select Register Bit7 Bit6 Bit5 Bits7-5: UNUSED. Read = 000b; Write = don’t care. Bits4-0: AMX0P4-0: AMUX0 Positive Input Selection AMX0P4-0 00000 00001 00010 00011 00100 00101 00110 ...
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C8051F320/1 Figure 5.6. AMX0N: AMUX0 Negative Channel Select Register Bit7 Bit6 Bit5 Bits7-5: UNUSED. Read = 000b; Write = don’t care. Bits4-0: AMX0N4-0: AMUX0 Negative Input Selection. Note that when GND is selected as ...
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Figure 5.7. ADC0CF: ADC0 Configuration Register R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the ...
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C8051F320/1 Figure 5.9. ADC0L: ADC0 Data Word LSB Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = ...
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Figure 5.10. ADC0CN: ADC0 Control Register R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for ...
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C8051F320/1 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...
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Figure 5.13. ADC0LTH: ADC0 Less-Than Data High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: High byte of ADC0 Less-Than Data Word. Figure 5.14. ADC0LTL: ADC0 Less-Than Data Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low ...
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C8051F320/1 5.4.1. Window Detector In Single-Ended Mode Figure 5.15 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF * (1023/1024) with respect to GND, and ...
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Window Detector In Differential Mode Figure 5.17 shows two example ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the mea- surable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are represented ...
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C8051F320/1 Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient DYNAMIC PERFORMANCE (10 kHz ...
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VOLTAGE REFERENCE The Voltage reference MUX on C8051F320/1 devices is configurable to use an externally connected voltage refer- ence, the internal reference voltage generator, or the power supply voltage VDD (see Figure 6.1). The REFSL bit in the Reference ...
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C8051F320/1 Figure 6.2. REF0CN: Reference Control Register R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. ...
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COMPARATORS C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in Figure 7.1; Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the following exceptions: (1) Their input selections differ as shown in Figure ...
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C8051F320/1 Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous out- put ...
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Figure 7.3. Comparator Hysteresis Plot CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Comparator hysteresis is programmed using Bits3-0 in the ...
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C8051F320/1 Figure 7.4. CPT0CN: Comparator0 Control Register R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: ...
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Figure 7.5. CPT0MX: Comparator0 MUX Selection Register R/W R/W R CMX0N1 CMX0N0 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bits5-4: CMX0N1-CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is ...
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C8051F320/1 Figure 7.6. CPT0MD: Comparator0 Mode Selection Register R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge ...
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Figure 7.7. CPT1CN: Comparator1 Control Register R/W R R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1-. 1: Voltage ...
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C8051F320/1 Figure 7.8. CPT1MX: Comparator1 MUX Selection Register R/W R/W R CMX1N1 CMX1N0 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bits5-4: CMX1N1-CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin ...
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Figure 7.9. CPT1MD: Comparator1 Mode Selection Register R/W R/W R CP1RIE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 rising-edge interrupt disabled. 1: Comparator1 rising-edge interrupt ...
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C8051F320/1 Table 7.1. Comparator Electrical Characteristics VDD = 3.0 V, -40°C to +85°C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. PARAMETER CP0+ - CP0- = 100 mV Response Time: † Mode 0, Vcm ...
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VOLTAGE REGULATOR (REG0) C8051F320/1 devices include a 5 V-to-3 V voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit ...
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C8051F320/1 8.1. Regulator Mode Selection REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is ...
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VBUS Detection When the USB Function Controller is used (see section page 143), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register REG0CN) indicates the current logic level of the VBUS signal. If enabled, ...
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C8051F320/1 Figure 8.1. REG0 Configuration: USB Bus-Powered VBUS From VBUS REGIN To 3V Power Net Figure 8.2. REG0 Configuration: USB Self-Powered From VBUS From 5V REGIN Power Net To 3V Power Net 70 C8051F320/1 VBUS Sense 5V In Voltage Regulator ...
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Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled C8051F320/1 VBUS From VBUS REGIN From 3V VDD Power Net Figure 8.4. REG0 Configuration: No USB Connection C8051F320/1 VBUS From 5V REGIN Power Net To 3V VDD Power Net C8051F320/1 VBUS Sense ...
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C8051F320/1 Figure 8.5. REG0CN: Voltage Regulator Control R/W R R/W REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 Bit7: REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit6: VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent (device ...
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CIP-51 MICROCONTROLLER The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of ...
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C8051F320/1 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to exe- cute, ...
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Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and ...
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C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND Register to A ANL A, direct AND direct byte to ...
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Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description MOV DPTR, #data16 Load DPTR with 16-bit constant MOVC A, @A+DPTR Move code byte relative DPTR to A MOVC A, @A+PC Move code byte relative MOVX A, @Ri Move ...
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C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two sepa- rate memory spaces: program memory and data memory. Program and data memory share the same address space ...
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C8051F320/1 9.2.2. Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a ...
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C8051F320/1 Table 9.3. Special Function Registers Register Address Description ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low AMX0N 0xBA AMUX0 Negative Channel Select AMX0P 0xBB AMUX0 Positive Channel Select B 0xF0 B Register CKCON 0x8E Clock Control CLKSEL 0xA9 Clock Select ...
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Table 9.3. Special Function Registers Register Address Description PCA0CPH3 0xEE PCA Capture 3High PCA0CPH4 0xFE PCA Capture 4 High PCA0CPL0 0xFB PCA Capture 0 Low PCA0CPL1 0xE9 PCA Capture 1 Low PCA0CPL2 0xEB PCA Capture 2 Low PCA0CPL3 0xED PCA ...
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C8051F320/1 Table 9.3. Special Function Registers Register Address Description VDM0CN 0xFF VDD Monitor Control XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 0x84-0x86, 0xAB-0xAF, 0xB4, 0xB5, 0xBF, 0xC7, 0xCE, Reserved 0xCF, 0xD2, 0xD3, 0xDF, ...
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Figure 9.5. SP: Stack Pointer R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults ...
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C8051F320/1 R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a second ...
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Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 16 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the spe- cific version ...
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C8051F320/1 9.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active ...
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Table 9.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 0x0003 (/INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (/INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B USB0 0x0043 ...
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C8051F320/1 9.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the ...
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Figure 9.10. IP: Interrupt Priority R/W R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 ...
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C8051F320/1 Figure 9.11. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ET3 ECP1 ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable ...
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Figure 9.12. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 PCP1 PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low ...
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C8051F320/1 Figure 9.13. EIE2: Extended Interrupt Enable 2 R/W R/W R Bit7 Bit6 Bit5 Bits7-1: UNUSED. Read = 0000000b. Write = don’t care. Bit0: EVBUS: Enable VBUS Level Interrupt. This bit sets the masking of the VBUS ...
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Figure 9.15. IT01CF: INT0/INT1 Configuration Register R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to Figure 19.4 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input ...
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C8051F320/1 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts, are ...
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Figure 9.16. PCON: Power Control Register R/W R/W R/W GF5 GF4 GF3 Bit7 Bit6 Bit5 Bits7-2: GF5-GF0: General Purpose Flags 5-0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit will ...
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C8051F320/1 98 Notes Rev. 1.1 ...
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RESET SOURCES Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
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C8051F320/1 10.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above V Power-On Reset delay (T ) occurs before the device is released from reset; this ...
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Power-Fail Reset / VDD Monitor When a power-down transition or power irregularity causes VDD to drop below V drive the /RST pin low and hold the CIP- reset state (see Figure 10.2). When VDD returns to a ...
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C8051F320/1 10.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the ...
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Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset. The state of the /RST pin is unaffected by this reset. 10.9. ...
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C8051F320/1 Figure 10.4. RSTSRC: Reset Source Register R/W R R/W USBRSF FERROR C0RSEF Bit7 Bit6 Bit5 Bit7: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a ...
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Table 10.1. Reset Electrical Characteristics -40°C to +85°C unless otherwise specified. PARAMETER I /RST Output Low Voltage OL /RST Input High Voltage /RST Input Low Voltage /RST Input Pull-Up Current /RST = 0.0 V VDD POR Threshold (V ) RST ...
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C8051F320/1 106 Notes Rev. 1.1 ...
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FLASH MEMORY On-chip, re-programmable FLASH memory is included for program code and non-volatile data storage. The FLASH memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the MOVX instruction. ...
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C8051F320/1 11.1.3. FLASH Write Procedure FLASH bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte FLASH page containing the target location, as described in Step 3. Write the first key ...
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Non-volatile Data Storage The FLASH memory can be used for non-volatile data storage as well as program code. This allows data such as cal- ibration coefficients to be calculated and stored at run time. Data is written using the ...
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C8051F320/1 Figure 11.1. FLASH Program Memory Map and Security Byte Locked when any other FLASH pages are locked Access limit set according to the FLASH security lock byte Figure 11.2. PSCTL: Program Store R/W Control R/W R/W R ...
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Figure 11.3. FLKEY: FLASH Lock and Key Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: FLKEY: FLASH Lock and Key Register Write: This register must be written to before FLASH writes or erases can be performed. FLASH remains locked until ...
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C8051F320/1 112 Notes Rev. 1.1 ...
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EXTERNAL RAM The C8051F320/1 devices include 2048 bytes of on-chip XRAM. This XRAM space is split into user RAM (addresses 0x0000 - 0x03FF) and USB0 FIFO space (addresses 0x0400 - 0x07FF). Figure 12.1. External Ram Memory Map 0xFFFF Same ...
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C8051F320/1 12.2. Accessing USB FIFO Space The upper 1k of XRAM functions as USB FIFO space. Figure 12.2 shows an expanded view of the FIFO space and user XRAM. FIFO space is accessed via USB FIFO registers; see for more ...
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Figure 12.3. EMI0CN: External Memory Interface Control R/W R/W R Bit7 Bit6 Bit5 Bits7-3: Not Used - reads 00000b. Bits2-0: PGSEL[2:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit ...
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C8051F320/1 116 Notes Rev. 1.1 ...
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OSCILLATORS C8051F320/1 devices include a programmable internal oscillator, an external oscillator drive circuit, and a 4x Clock Multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 13.1. The system ...
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C8051F320/1 On C8051F320/1 devices, OSCICL is factory calibrated to obtain a 12 MHz base frequency (f details oscillator programming for C8051F320/1 devices. Electrical specifications for the precision internal oscillator are given in Table 13.3 on page 126. Note that the ...
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Figure 13.2. OSCICN: Internal Oscillator Control Register R/W R R/W IOSCEN IFRDY SUSPEND Bit7 Bit6 Bit5 Bit7: IOSCEN: Internal Oscillator Enable Bit. 0: Internal Oscillator Disabled. 1: Internal Oscillator Enabled. Bit6: IFRDY: Internal Oscillator Frequency Ready Flag. 0: Internal Oscillator ...
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C8051F320/1 13.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must ...
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External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however ...
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C8051F320/1 Figure 13.4. OSCXCN: External Oscillator Control Register R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: ...
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Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB com- munication (see Section “15.4. USB Clock Configuration” on page put can also be used as ...
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C8051F320/1 13.4. System and USB Clock Selection The internal oscillator requires little start-up time and may be selected as the system or USB clock immediately fol- lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators ...
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Figure 13.6. CLKSEL: Clock Select Register R/W R/W R/W - USBCLK Bit7 Bit6 Bit5 Bit 7: Unused. Read = 0b; Write = don’t care. Bits6-4: USBCLK2-0: USB Clock Select These bits select the clock supplied to USB0. When operating USB0 ...
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C8051F320/1 Table 13.3. Internal Oscillator Electrical Characteristics -40°C to +85°C unless otherwise specified PARAMETER Internal Oscillator Frequency Internal Oscillator Supply Current (from VDD) † USB Clock Frequency † Applies only to external oscillator sources. 126 CONDITIONS MIN Reset Frequency 11.82 ...
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PORT INPUT/OUTPUT Digital and analog resources are available through 25 I/O pins (C8051F320 I/O pins (C8051F321). Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) ...
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C8051F320/1 Figure 14.2. Port I/O Cell Block Diagram /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT ANALOG INPUT PORT-INPUT 128 VDD GND Analog Select Rev. 1.1 VDD (WEAK) PORT PAD ...
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Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding ...
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C8051F320/1 Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped P0 SF Signals PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI ...
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Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or ...
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C8051F320/1 Figure 14.5. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP1AE CP1E CP0AE Bit7 Bit6 Bit5 Bit7: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. Bit6: CP1E: ...
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Figure 14.6. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input or push-pull ...
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C8051F320/1 14.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general pur- pose I/O. Ports3-0 are accessed through corresponding special function registers (SFRs) that are ...
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Figure 14.7. P0: Port0 Register R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7-0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance ...
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C8051F320/1 Figure 14.9. P0MDOUT: Port0 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n ...
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Figure 14.11. P1: Port1 Register R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7-0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance ...
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C8051F320/1 Figure 14.13. P1MDOUT: Port1 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n ...
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Figure 14.15. P2: Port2 Register R/W R/W R/W P2.7 P2.6 P2.5 Bit7 Bit6 Bit5 Bits7-0: P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance ...
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C8051F320/1 Figure 14.17. P2MDOUT: Port2 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P2.7-P2.0 (respectively): ignored if corresponding bit in register P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n ...
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Figure 14.19. P3: Port3 Register R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits7-0: P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). Read ...
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C8051F320/1 Figure 14.21. P3MDOUT: Port3 Output Mode Register R/W R/W R Bit7 Bit6 Bit5 Bits7-1: UNUSED. Read = 0000000b; Write = don’t care. Bit0: Output Configuration Bit for P3.0; ignored if corresponding bit in register P3MDIN is ...
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UNIVERSAL SERIAL BUS CONTROLLER (USB0) C8051F320/1 devices include a complete Full/Low Speed USB function for USB peripheral implementations†. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), ...
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C8051F320/1 15.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 15.1. Endpoint Addressing Scheme ...
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Figure 15.2. USB0XCN: USB0 Transceiver Control R/W R/W R/W PREN PHYEN SPEED PHYTST1 PHYTST0 Bit7 Bit6 Bit5 Bit7: PREN: Internal Pull-up Resistor Enable The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit. 0: Internal ...
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C8051F320/1 15.3. USB Register Access The USB0 controller registers listed in Table 15.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. ...
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Figure 15.4. USB0ADR: USB0 Indirect Address Register R/W R/W R/W BUSY AUTORD Bit7 Bit6 Bit5 Bits7: BUSY: USB0 Register Read Busy Flag This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to initiate ...
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C8051F320/1 Figure 15.5. USB0DAT: USB0 Data Register R/W R/W R/W Bit7 Bit6 Bit5 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB0ADR.7) => ‘0’. 2. Load the target USB0 register address ...
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Table 15.2. USB0 Controller Registers USB Register USB Register Name Address IN1INT 0x02 OUT1INT 0x04 CMINT 0x06 IN1IE 0x07 OUT1IE 0x09 CMIE 0x0B FADDR 0x00 POWER 0x01 FRAMEL 0x0C FRAMEH 0x0D INDEX 0x0E CLKREC 0x0F FIFOn 0x20-0x23 E0CSR 0x11 EINCSRL ...
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C8051F320/1 15.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must ...
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FIFO Management 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 15.8. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split ...
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C8051F320/1 Split Mode is not enabled, double-buffering may be enabled for the entire endpoint FIFO. See Table 15.3 for a list of maximum packet sizes for each FIFO configuration. Table 15.3. FIFO Configurations Endpoint Split Mode Number Enabled? 0 N/A ...
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Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not ...
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C8051F320/1 15.7. Function Configuration and Control The USB register POWER (Figure 15.11) is used to configure and control USB0 at the device level (enable/disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit (POWER.3) is set to ‘1’ by hardware when ...
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Figure 15.11. POWER: USB0 Power (USB Register) R/W R/W R/W ISOUD - - Bit7 Bit6 Bit5 Bit7: ISOUD: ISO Update This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = ‘1’, USB0 will send the packet when ...
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C8051F320/1 Figure 15.12. FRAMEL: USB0 Frame Number Low (USB Register Bit7 Bit6 Bit5 Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. Figure 15.13. FRAMEH: USB0 Frame Number High (USB Register) R ...
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Interrupts The read-only USB0 interrupt flags are located in the USB registers shown in Figure 15.14 through Figure 15.16. The associated interrupt enable bits are located in the USB registers shown in Figure 15.17 through Figure 15.19. A USB0 ...
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C8051F320/1 Figure 15.15. OUT1INT: USB0 Out Endpoint Interrupt (USB Register Bit7 Bit6 Bit5 Bits7-4: Unused. Read = 0000b. Write = don’t care. Bit3: OUT3: OUT Endpoint 3 Interrupt-pending Flag This bit is cleared when ...
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Figure 15.16. CMINT: USB0 Common Interrupt (USB Register Bit7 Bit6 Bit5 Bits7-4: Unused. Read = 0000b; Write = don’t care. Bit3: SOF: Start of Frame Interrupt Set by hardware when a SOF token is ...
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C8051F320/1 Figure 15.17. IN1IE: USB0 IN Endpoint Interrupt Enable (USB Register) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 ...
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Figure 15.19. CMIE: USB0 Common Interrupt Enable (USB Register) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: Unused. Read = 0000b; Write = don’t care. Bit3: SOFE: Start of Frame Interrupt Enable 0: SOF interrupt disabled. 1: SOF ...
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C8051F320/1 Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to ‘1’ and ...
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OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will ...
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C8051F320/1 Figure 15.20. E0CSR: USB0 Endpoint0 Control (USB Register) R/W R/W R/W SSUEND SOPRDY SDSTL Bit7 Bit6 Bit5 Bit7: SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware ...
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Figure 15.21. E0CNT: USB0 Endpoint 0 Data Count (USB Register Bit7 Bit6 Bit5 Bit7: Unused. Read = 0; Write = don’t care. Bits6-0: E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received ...
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C8051F320/1 15.11. Configuring Endpoints1-3 Endpoints1-3 are configured and controlled through their own sets of the following control/status registers: IN regis- ters EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of endpoint control/ status registers is mapped ...
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IN Isochronous Mode When the ISO bit (EINCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode. Once an end- point has been configured for ISO IN mode, the host will send one IN token (data ...
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C8051F320/1 Figure 15.22. EINCSRL: USB0 IN Endpoint Control High Byte (USB Register R/W - CLRDT STSTL Bit7 Bit6 Bit5 Bit7: Unused. Read = 0; Write = don’t care. Bit6: CLRDT: Clear Data Toggle. Write: Software should write ‘1’ ...
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Figure 15.23. EINCSRH: USB0 IN Endpoint Control Low Byte (USB Register) R/W R/W R/W DBIEN ISO DIRSEL Bit7 Bit6 Bit5 Bit7: DBIEN: IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected ...
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C8051F320/1 15.13. Controlling Endpoints1-3 OUT Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in ...
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Figure 15.24. EOUTCSRL: USB0 OUT Endpoint Control High Byte (USB Register) W R/W R/W CLRDT STSTL SDSTL Bit7 Bit6 Bit5 Bit7: CLRDT: Clear Data Toggle Write: Software should write ‘1’ to this bit to reset the OUT endpoint data toggle ...
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C8051F320/1 Figure 15.25. EOUTCSRH: USB0 OUT Endpoint Control Low Byte (USB Register) R/W R/W R/W DBOEN ISO - Bit7 Bit6 Bit5 Bit7: DBOEN: Double-buffer Enable 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT ...
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Table 15.4. USB Transceiver Electrical Characteristics VDD = 3.0 to 3.6V, -40°C to +85°C unless otherwise specified PARAMETERS SYMBOL TRANSMITTER V Output High Voltage OH V Output Low Voltage OL V Output Crossover Point CRS Z Output Impedance DRV R ...
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C8051F320/1 174 Notes Rev. 1.1 ...
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SMBUS The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Manage- ment Bus Specification, version 1.1, and compatible with the I system controller are byte oriented with the SMBus interface autonomously ...
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C8051F320/1 16.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification ...
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SMBus Operation Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device ini- tiates ...
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C8051F320/1 16.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I bilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. ...
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Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following applica- tion-independent ...
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C8051F320/1 16.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the ...
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Figure 16.4 shows the typical SCL generation described by Equation 16.2. Notice that T large The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower LOW slave ...
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C8051F320/1 Figure 16.5. SMB0CF: SMBus Clock/Configuration Register R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins. 0: SMBus interface ...
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SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see Figure 16.6). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump ...
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C8051F320/1 Figure 16.6. SMB0CN: SMBus Control Register R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: ...
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Table 16.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: • A START is generated. MASTER • START is generated. • SMB0DAT is written before the start of an SMBus TXMODE frame. STA • A START followed ...
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C8051F320/1 16.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...
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SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...
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C8051F320/1 16.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the ...
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Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the inter- face enters Slave Receiver Mode when a START followed by a slave address ...
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C8051F320/1 16.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START ...
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SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response ...
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C8051F320/1 Table 16.4. SMBus Status Decoding VALUES READ CURRENT SMBUS STATE A slave byte was transmitted; NACK received. A slave byte was transmitted; ACK 0100 received. A Slave byte was transmitted; error 0 1 ...
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UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in “17.1. Enhanced ...
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C8051F320/1 17.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...
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Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. Figure 17.3. UART Interconnect Diagram 17.2.1. 8-Bit UART 8-Bit UART ...
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C8051F320/1 17.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data ...
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Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave pro- cessors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, ...
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C8051F320/1 Figure 17.7. SCON0: Serial Port 0 Control Register R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: ...
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Figure 17.8. SBUF0: Serial (UART0) Port Data Buffer Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SBUF0[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is ...
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C8051F320/1 Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Frequency: 24.5 MHz Target Baud Rate Baud Rate % Error (bps) 230400 -0.32% 115200 -0.32% 57600 0.15% 28800 -0.32% 14400 0.15% 9600 -0.32% 2400 -0.32% 1200 0.15% ...