MC68HC908GT8CFB Freescale Semiconductor, MC68HC908GT8CFB Datasheet
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MC68HC908GT16 MC68HC908GT8 MC68HC08GT16 Data Sheet M68HC08 Microcontrollers MC68HC908GT16 Rev. 5.0 04/2007 freescale.com ...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2007. All rights reserved. ...
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... Figure 14-18. ESCI Prescaler Register (SCPSC) — Corrected address location MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 4 Description and V ) — Corrected connections REFH REFL ) — Corrected connections REFH ) — Corrected connections REFL Page Number(s) N/A 77 211 211 212 214 143 148 151 50 170 171 Throughout 57 172 Freescale Semiconductor ...
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... Figure 19-10. Forced Monitor Mode (Low) Figure 19-11. Forced Monitor Mode (High) Figure 19-12. Standard Monitor Mode MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Description — In the description of the COP Rate Select Bit — Replaced BUSCLKX4 with COPCLK — ...
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... Revision History MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 6 Freescale Semiconductor ...
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... Chapter 16 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Chapter 17 Timebase Module (TBM 217 Chapter 18 Timer Interface Module (TIM 221 Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 275 Appendix A MC68HC08GT16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 7 ...
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... List of Chapters MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 8 Freescale Semiconductor ...
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... Flash Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.7 Flash Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.8 ICG User Trim Registers (ICGTR5 and ICGTR3 2.6.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.6.10 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Chapter 1 General Description and and DDA SSA and V ) ...
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... Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.7 COPD (COP Disable 5.3.8 COPRS (COP Rate Select 5.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 10 Chapter 3 Analog-to-Digital Converter (ADC DDA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SSA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 REFL ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Chapter 4 Configuration Register (CONFIG) Chapter 5 Freescale Semiconductor ...
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... Clock Monitor Reference Generator 7.3.4.2 Internal Clock Activity Detector 7.3.4.3 External Clock Activity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.3.5 Clock Selection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3.5.1 Clock Selection Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3.5.2 Clock Switching Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Chapter 6 Central Processor Unit (CPU) Chapter 7 11 ...
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... IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.2 Features 107 9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.4 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 12 Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) Freescale Semiconductor ...
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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.7 External Interrupt Module (IRQ 119 11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Chapter 10 Low-Voltage Inhibit (LVI) Chapter 11 Low-Power Modes (MODES) 13 ...
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... Data Direction Register 133 12.5.3 Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.6 Port 134 12.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.6.2 Data Direction Register 135 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 14 Chapter 12 Input/Output (I/O) Ports (PORTS) Freescale Semiconductor ...
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... Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Chapter 13 Resets and Interrupts Chapter 14 15 ...
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... Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.3.2.6 Monitor Mode Entry Module Reset (MODRST 185 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 16 Chapter 15 System Integration Module (SIM) Freescale Semiconductor ...
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... SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.11 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.11.1 MISO (Master In/Slave Out 211 16.11.2 MOSI (Master Out/Slave In 211 16.11.3 SPSCK (Serial Clock 211 16.11.4 SS (Slave Select 212 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Chapter 16 17 ...
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... TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 18.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 18.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 18.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 18 Chapter 17 Timebase Module (TBM) Chapter 18 Timer Interface Module (TIM) Freescale Semiconductor ...
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... Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 20.14 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 20.15 Typical Supply Currents 267 20.16 ADC Characteristics 268 20.17 5.0-V SPI Characteristics 269 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Chapter 19 Development Support Chapter 20 Electrical Specifications 19 ...
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... DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 A.8.3 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 A.9 ADC Characteristics 288 A.9.1 Internal Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 A.9.2 Memory Characteristics 289 A.10 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 20 Chapter 21 Appendix A MC68HC08GT16 and 284 REFH REFL Freescale Semiconductor ...
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... On-chip programming firmware for use with host personal computer which does not require high voltage for entry • In-system programming (ISP security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the Flash difficult for unauthorized users. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor (1) Appendix A MC68HC08GT16. 21 ...
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... Port bits: PTD0–PTD7; dual 2-channel TIM modules • Specific features of the MC68HC908GT16 in 44-pin QFP are: – Port bits: PTC0–PTC6 – Port bits: PTD0–PTD7; dual 2-channel TIM modules MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 22 Freescale Semiconductor ...
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... Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908GT16. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor MCU Block Diagram 23 ...
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... PTA7/KBD7– (1) PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1)(2) PTC4 (1)(2) PTC3 (1)(2) PTC2 (1)(2) PTC1 (1)(2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
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... Pin Assignments V (ADC/ICG) DDA V (ADC/ICG) SSA PTE3/OSC2 PTE4/OSC1 PTE0/TxD PTE1/RxD PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK PTD4/T1CH0 Figure 1-2. 42-Pin SDIP Pin Assignments MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor PTE2 RST 6 37 PTC0 7 36 PTC1 8 35 PTC2 ...
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... C1 optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5 and PTA1/KBD1 33 PTA0/KBD0 REFL V 30 REFH PTB7/AD7 29 PTB6/AD6 28 PTB5/AD5 27 PTB4/AD4 26 PTB3/AD3 25 PTB2/AD2 24 PTB1/AD1 23 Figure 1-4 Freescale Semiconductor ...
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... ADC and should be filtered. V potential as the analog supply pin, V externally filtered. V must be connected to the same voltage potential as the analog supply pin V REFL See Chapter 3 Analog-to-Digital Converter MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor MCU 0.1 μ ...
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... Chapter 12 Input/Output (I/O) Ports (PORTS) (KBI). (PORTS). Chapter 18 Timer Interface Module Chapter 12 Input/Output (I/O) Ports Chapter 14 Enhanced Serial Communications Interface (PORTS). (PORTS). NOTE ). Although the I/O ports do not require termination, SS and and Chapter 3 (TIM), Chapter 16 Serial (PORTS). Chapter 4 Configuration Freescale Semiconductor ...
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... BRKH • $FE0A; break address register low, BRKL • $FE0B; break status and control register, BRKSCR MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Figure 2-1, includes: (Figure 2-1) Figure 2-1 and ...
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... BYTES 41,440 BYTES FLASH MEMORY 15,872 BYTES RESERVED Figure 2-1. Memory Map $C000 (1) ↓ RESERVED $DFFF FLASH MEMORY $E000 ↓ MC68HC908GT8 7,680 BYTES $FDFF 1. Inadvertent access to these locations will not cause an illegal address reset. Figure is continued on the next page Freescale Semiconductor ...
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... FLASH VECTORS ↓ (2) $FFFF 2. $FFF6–$FFFD reserved for eight security bytes MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 3 BYTES 16 BYTES MONITOR ROM 304 BYTES 46 BYTES 90 BYTES 36 BYTES Figure 2-1. Memory Map (Continued) Input/Output (I/O) Section ...
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... PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 PSSB3 PSSB2 PSSB1 PSSB0 AFIN ARUN AOVFL ARD8 ARD3 ARD2 ARD1 ARD0 DDRE3 DDRE2 DDRE1 DDRE0 Unaffected Freescale Semiconductor ...
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... Write: See page 171. Reset: Read: ESCI Baud Rate Register $0019 (SCBR) Write: See page 171. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Bit PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 ...
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... MS0B MS0A Unimplemented R = Reserved Bit 0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 TBIE TBON R TACK IRQF1 0 IMASK1 MODE1 ACK1 EXT- OSCENIN- R CLKEN STOP SSREC STOP COPD PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Unaffected Freescale Semiconductor ...
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... See page 236. Reset: Read: Timer 2 Channel 0 $0032 Register Low (T2CH0L) Write: See page 236. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Bit Bit Indeterminate after reset Bit 7 ...
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... ADIV2 ADIV1 ADIV0 ADICLK Unimplemented R = Reserved Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 ICGS ECGS ICGON ECGON TRIM3 TRIM2 TRIM1 TRIM0 DDIV3 DDIV2 DDIV1 DDIV0 DSTG3 DSTG2 DSTG1 DSTG0 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 Unaffected Freescale Semiconductor ...
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... Write: See page 241. Reset: Read: Break Status and Control $FE0B Register (BRKSCR) Write: See page 241. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Bit POR ...
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... TRIM6 TRIM5 TRIM4 Unaffected by reset TRIM7 TRIM6 TRIM5 TRIM4 Unaffected by reset Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved Bit BPR3 BPR2 BPR1 BPR0 TRIM3 TRIM2 TRIM1 TRIM0 TRIM3 TRIM2 TRIM1 TRIM0 U = Unaffected Freescale Semiconductor ...
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... Vector Priority Lowest Highest MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor . Table 2-1. Vector Addresses Vector Address $FFDC Timebase Vector (High) IF16 $FFDD Timebase Vector (Low) $FFDE ADC Conversion Complete Vector (High) IF15 $FFDF ADC Conversion Complete Vector (Low) ...
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... ICG user trim register (ICGTR5) ; • $FF81 ICG user trim register (ICGTR3) • $FFDC–$FFFF; these locations are reserved for user-defined interrupt and reset vectors MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 40 NOTE NOTE NOTE Freescale Semiconductor ...
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... Use the following procedure to erase a page (64 bytes) of Flash memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 36-byte user interrupt vectors area also forms a page. Any Flash memory page can be erased alone. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...
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... When in monitor mode, with security sequence failed (see of any Flash address. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 42 NOTE CAUTION (1) within the Flash memory address range. NOTE NOTE 19.3.2 Security), write to the Flash block protect register instead Freescale Semiconductor ...
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... Do not exceed t Characteristics. 1. The time between each Flash address change, or the time between the last Flash address programmed to clearing PGM bit, must not exceed the maximum programming time, t MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor CAUTION NOTE (1) . ...
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... NVS 5 SET HVEN BIT 6 WAIT FOR A TIME, t PGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, t PROG COMPLETED Y PROGRAMMING THIS ROW CLEAR PGM BIT WAIT FOR A TIME, t NVH CLEAR HVEN BIT WAIT FOR A TIME, t RCV END OF PROGRAMMING Freescale Semiconductor ...
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... Flash memory. START ADDRESS OF FLASH BLOCK PROTECT Figure 2-6. Flash Block Protect Start Address MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NOTE , present on the IRQ pin. This voltage also allows entry TST 6 5 ...
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... FLBPR and vectors are protected $FF80 (1111 1111 1000 0000) — FFFF Vectors are protected The entire Flash memory is not protected. NOTE TRIM6 TRIM5 TRIM4 TRIM3 Unaffected by reset. Initial value from factory Bit 0 TRIM2 TRIM1 TRIM0 Freescale Semiconductor ...
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... Flash, otherwise the operation will discontinue, and the Flash will be on standby mode Standby mode is the power saving mode of the Flash module in which all internal control signals to the Flash are inactive and the current consumption of the Flash minimum. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NOTE Flash Memory 47 ...
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... Memory MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 48 Freescale Semiconductor ...
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... I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC will return a 0. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 3-2. 49 ...
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... PTA7/KBD7– (1) PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1)(2) PTC4 (1)(2) PTC3 (1)(2) PTC2 (1)(2) PTC1 (1)(2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
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... REFL straight-line linear conversion. The ADC input voltage must always be greater than must always be greater than or equal to V DDA REFH MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor DDRBx PTBx DISABLE ADC DATA REGISTER ADC VOLTAGE IN (V ADIN ...
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... ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the WAIT instruction. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 52 NOTE pin to the same voltage potential as the V pin to the same voltage potential as the ADC cycles ADC frequency pin, and DD pin. The SS Freescale Semiconductor ...
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... For maximum noise immunity, route place bypass capacitors as close as possible to the package. SS Routing V close and parallel to V REFH noise rejection. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ) DDA as its power pin. Connect the V DDA NOTE carefully and place bypass DDA ) SSA as its ground pin ...
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... Only one conversion is completed between writes to the ADSCR when this bit is cleared. Reset clears the ADCO bit Continuous ADC conversion 0 = One ADC conversion MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5 AIEN ADCO ADCH4 ADCH3 NOTE 2 1 Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor ...
Page 55
... One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes. Address: $003D Bit 7 Read: AD7 Write: Reset: 0 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Table 3-1. NOTE Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ...
Page 56
... Table 3-2. ADC Clock Divide Ratio ADIV1 ADIV0 ADC Clock Rate ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ (1) (1) ADC input clock ÷ bus frequency CGMXCLK = ADIV[2: Bit 20.16 ADC Characteristics. ≅ 1 MHz Freescale Semiconductor ...
Page 57
... POR (power-on reset). The CONFIG registers are not in the Flash memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NOTE Figure 4-1 and Figure 4-2 ...
Page 58
... EXTXTALEN EXTSLOW EXTCLKEN Reserved LVIRSTD LVIPWRD LVI5OR3 See Note Table 4-1 for configuration options for the external source. See for a more detailed description of the external clock Chapter 7 Internal Clock Generator (ICG) NOTE 2 1 Bit 0 0 OSCENINSTOP Bit 0 SSREC STOP COPD Freescale Semiconductor ...
Page 59
... LVI disabled during stop mode LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. See 1 = LVI module resets disabled 0 = LVI module resets enabled MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Pin Function PTE3/OSC2 PTE4 PTE3 Default setting — ...
Page 60
... COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 60 Chapter 10 Low-Voltage Inhibit NOTE NOTE Chapter 5 Computer Operating Properly (COP) (LVI). Chapter 10 Low-Voltage Inhibit . See Chapter 20 DD Module. Freescale Semiconductor ...
Page 61
... COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 5-1 ...
Page 62
... Internal Reset An internal reset clears the COP prescaler and the COP counter. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 62 NOTE . During the break state, TST NOTE Figure 5-1. 5.4 COP Control Register) clears the COP 7.3.5 Freescale Semiconductor ...
Page 63
... Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Low byte of reset vector ...
Page 64
... STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset. 5.8 COP Module During Break Mode The COP is disabled during a break interrupt when V MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5 present on the RST pin. TST Freescale Semiconductor ...
Page 65
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 6.3 CPU Registers Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 65 ...
Page 66
... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers Unaffected by reset Figure 6-2. Accumulator ( Figure 6-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...
Page 67
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...
Page 68
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5 NOTE 2 1 Bit Freescale Semiconductor ...
Page 69
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 69 ...
Page 70
... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 – – IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 – – IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
Page 71
... CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← ...
Page 72
... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 – – – IX1 SP1 9E6C ff 5 Freescale Semiconductor ...
Page 73
... ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...
Page 74
... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...
Page 75
... Memory location N Negative bit 6.8 Opcode Map See Table 6-2. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← ...
Page 76
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 77
... The ICG, shown in Figure 7-2, contains these major submodules: • Clock enable circuit • Internal clock generator • External clock generator • Clock monitor circuit • Clock selection circuit MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NOTE 77 ...
Page 78
... PTA7/KBD7– (1) PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1)(2) PTC4 (1)(2) PTC3 (1)(2) PTC2 (1)(2) PTC1 (1)(2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 79
... ECGON ICGON EXTXTALEN EXTSLOW INTERNAL LOGIC TO MCU EXTERNAL NAME CONFIG2 REGISTER BIT NAME TOP LEVEL SIGNAL MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor CLOCK SELECTION CIRCUIT CLOCK MONITOR CIRCUIT INTERNAL CLOCK GENERATOR CLOCK/PIN ENABLE CIRCUIT EXTERNAL CLOCK ...
Page 80
... A frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators • A digital loop filter MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 80 Figure 7-3, creates a low frequency base clock (IBASE), which ) of 307.2 kHz ± 25 percent, and an internal clock (ICLK) which is NOM Freescale Semiconductor ...
Page 81
... ICLK is passed through to IBASE undivided. When the internal clock generator is stable, the frequency of IBASE will be equal to the nominal frequency (f kHz ± 25 percent. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ++ + DIGITAL LOOP FILTER – ...
Page 82
... Maximum $x00 to $x08 Minimum $xDF to $xFF +32 (+$020) Maximum $x00 to $x20 Relative Correction (1) in DCO –2/31 –6.45% –2/19 –10.5% –0.5/31 –1.61% –0.5/17.5 –2.86% –0.0625/31 –0.202% –0.0625/17.0625 –0.366% +0.0625/30.9375 +0.202% +0.0625/17 +0.368% +0.5/30.5 +1.64% +0.5/17 +2.94% +2/29 +6.90% +2/17 +11.8% Freescale Semiconductor ...
Page 83
... Clock Enable desired. When enabled, the amplifier will be connected between the PTE4/OSC1 and PTE3/OSC2 pins. Otherwise, the PTE3/OSC2 pin reverts to its port function. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor AMPLIFIER EXTERNAL CLOCK GENERATOR ...
Page 84
... Each signal (IBASE and ECLK) is always divided by four. A longer divider is used on either IBASE or ECLK based on the EXTSLOW bit. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 84 Figure 7-4 to follow strict Pierce oscillator guidelines and may not Figure 7-5, contains these blocks: NOTE Table 7-2. Freescale Semiconductor ...
Page 85
... Since this will change the EREF and IREF divide ratios important to turn the clock monitor off (CMON = 0) after inactivity is detected to ensure valid recovery. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor CMON FICGS ...
Page 86
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 86 Figure 7-6, looks for at least one falling edge on the DFFRS DFFRR CONFIG2 REGISTER BIT TOP LEVEL SIGNAL Figure 7-7, looks for at least one falling edge on the external IOFF ICGS DFFRR CK R NAME REGISTER BIT NAME MODULE SIGNAL Freescale Semiconductor ...
Page 87
... CS ICLK ECLK IOFF EOFF RESET V SS ECGON NAME NAME Figure 7-8. Clock Selection Circuit Block Diagram MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor DFFRS DFFRR ...
Page 88
... Using clock monitor interrupts • Quantization error in digitally controlled oscillator (DCO) output • Switching internal clock frequencies • Nominal frequency settling time • Improving frequency settling time • Trimming frequency MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 88 Freescale Semiconductor ...
Page 89
... These events must happen in sequence. A short assembly code example of how to employ this flow is shown in Figure 7-10. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ; turn on external oscillator ; wait until external clock engaged ; select external clock for bus ; turn off internal clock (if desired) ...
Page 90
... DDIV and DSTG, the output of the DCO can change only in MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5 turn on external oscillator ; (assumes internal osc is on) ; wait until external clock engaged ; select external clock for bus ; enable Clock Monitor ; enable CM interrupt Freescale Semiconductor ...
Page 91
... The value of the binary weighted divider does not affect the relative change in output clock period for a given change in DSTG[7:5]. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 7-2. Table 7-2. Quantization Error in ICLK ...
Page 92
... The time that the ICLK takes to adjust to the correct period is known as the settling time. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 92 7.4.1 Switching Clock 7.4.1 Switching Clock Sources), if desired. 7.4.2 Enabling the Clock Monitor), if desired. Sources). Freescale Semiconductor ...
Page 93
... Additionally, other process factors and noise can affect the actual tolerances of the points at which the filter changes modes. This means a worst case adjustment percent (ICLK MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor . The period of ICLK, however, will vary as the corrections occur. ICLK – ...
Page 94
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 94 τ τ 430 μs 1/ (25.8 MHz) 84 107 μs 1/ (6.45 MHz) 21 141 μs 1/ (307.2 kHz (25.8 MHz) 84 11.9 ms τ τ 5 tot 535 μs 850 μs 212 μs 525 μs 246 μs 560 μs 12.0 ms 12.3 ms Freescale Semiconductor ...
Page 95
... When EXTXTALEN is clear, the stabilization divider is configured to 16 cycles since an external clock source does not need a startup time. The default state for this option is clear. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Chapter 4 Configuration Register (CONFIG) CONFIG2 Options on ...
Page 96
... Write: See page 99. Reset: Figure 7-11. ICG Module I/O Register Summary MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 96 Figure 7-11. These registers are: Bit CMF CMIE CMON CS ( Unimplemented Bit 0 ICGS ECGS ICGON ECGON Reserved U = Unaffected Freescale Semiconductor ...
Page 97
... Register bit is temporarily forced clear or set (respectively) in the given condition. (0), (1) Register bit must be clear or set (respectively) for the given condition to occur. us, uc, uw Register bit cannot be set, cleared, or written (respectively) in the given condition. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Bit ...
Page 98
... ECGON is clear, or during reset External clock (ECLK) sources CGMXCLK 0 = Internal clock (ICLK) sources CGMXCLK MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5 CMF CMON CS ICGON ( Bit 0 ICGS ECGS ECGON Freescale Semiconductor ...
Page 99
... A value of $00 in this register is interpreted the same as a value of $01. This register cannot be written when the CMON bit is set. Reset sets this factor to $15 (decimal 21) for default frequency of 6.45 MHz ± 25 percent (1.613 MHz ± 25 percent bus). MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...
Page 100
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 100 TRIM6 TRIM5 TRIM4 TRIM3 Figure 7-14. ICG Trim Register (ICGTR DDIV3 Unaffected DSTG6 DSTG5 DSTG4 DSTG3 Unaffected by reset 2 1 Bit 0 TRIM2 TRIM1 TRIM0 Bit 0 DDIV2 DDIV1 DDIV0 Bit 0 DSTG2 DSTG1 DSTG0 Freescale Semiconductor ...
Page 101
... When an interrupt pin is both falling-edge and low-level triggered, the interrupt remains set until both of these events occur: • Vector fetch or software clear • Return of the interrupt pin to logic 1 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 101 ...
Page 102
... PTA7/KBD7– (1) PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1)(2) PTC4 (1)(2) PTC3 (1)(2) PTC2 (1)(2) PTC1 (1)(2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 103
... Software may generate the interrupt acknowledge signal by writing the ACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor V DD CLR ...
Page 104
... Controls triggering sensitivity of the IRQ interrupt pin Address: $001D Bit 7 Read: Write: Reset Unimplemented Figure 8-4. IRQ Status and Control Register (INTSCR) MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 104 NOTE Support IRQF Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...
Page 105
... This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor IRQ Status and Control Register 105 ...
Page 106
... External Interrupt (IRQ) MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 106 Freescale Semiconductor ...
Page 107
... If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 107 ...
Page 108
... PTA7/KBD7– (1) PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1)(2) PTC4 (1)(2) PTC3 (1)(2) PTC2 (1)(2) PTC1 (1)(2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 109
... Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor RESET V DD CLR ...
Page 110
... Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 110 NOTE Freescale Semiconductor ...
Page 111
... These read-only bits always read as 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit Keyboard interrupt pending keyboard interrupt pending MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 9.7.1 Keyboard Status and Control ...
Page 112
... Reset clears the keyboard interrupt enable register PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 112 . KBIE6 KBIE5 KBIE4 KBIE3 Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
Page 113
... V which will re-trigger the power-on reset and reset the trip point to 3-V operation. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI ...
Page 114
... In the configuration register, the DD TRIPF fall below V ), the LVI will maintain a reset condition until DD TRIPF . This prevents a condition in which the MCU is TRIPR , which causes the MCU to exit TRIPR LVISTOP FROM CONFIG1 LVI RESET level, software can monitor V DD Freescale Semiconductor Figure Bit polling ...
Page 115
... Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor is approximately equal HYS ...
Page 116
... Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 116 Freescale Semiconductor ...
Page 117
... If enabled, the break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor (CONFIG).) Chapter 4 Configuration ...
Page 118
... The clock monitor is disabled (CMON = 0) which will also clear the clock monitor interrupt enable (CMIE) and clock monitor flag (CMF) bits. The CS, ICGON, ECGON, N, TRIM, DDIV, and DSTG bits are unaffected. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 118 Freescale Semiconductor ...
Page 119
... If enabled, the low-voltage inhibit (LVI) module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Computer Operating Properly Module (COP) 119 ...
Page 120
... The timer interface modules (TIM) remain active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 120 Freescale Semiconductor ...
Page 121
... TIM1 overflow – $FFF4 and $FFF5; TIM1 channel 1 – $FFF6 and $FFF7; TIM1 channel 0 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Timebase Module (TBM) voltage resets TRIPF 121 ...
Page 122
... Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 122 TRIPF NOTE voltage resets the Freescale Semiconductor ...
Page 123
... Data Direction Register A $0004 (DDRA) Write: See page 126. Reset: Read: Data Direction Register B $0005 (DDRB) Write: See page 128. Reset: MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NOTE Bit PTA7 PTA6 PTA5 PTB7 PTB6 PTB5 0 PTC6 PTC5 ...
Page 124
... PTAPUE5 PTAPUE4 PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0 PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 Unimplemented Bit 0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Freescale Semiconductor ...
Page 125
... DDRD4 5 DDRD5 6 DDRD6 7 DDRD7 0 DDRE0 1 DDRE1 2 DDRE2 E 3 DDRE3 4 DDRE4 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor DDR Module Control KBIE0 KBIE1 KBIE2 KBIE3 KBD KBIE4 KBIE5 KBIE6 KBIE7 ADC ADCH4–ADCH0 SPI SPE ELS0B:ELS0A TIM1 ELS1B:ELS1A ...
Page 126
... PTA6 PTA5 PTA4 PTA3 Unaffected by reset KBD6 KBD5 KBD4 KBD3 Figure 12-2. Port A Data Register (PTA) Chapter 9 Keyboard Interrupt Module (KBI DDRA6 DDRA5 DDRA4 DDRA3 NOTE 2 1 Bit 0 PTA2 PTA1 PTA0 KBD2 KBD1 KBD0 2 1 Bit 0 DDRA2 DDRA1 DDRA0 Freescale Semiconductor ...
Page 127
... Read: PTAPUE7 Write: Reset: 0 Figure 12-5. Port A Input Pullup Enable Register (PTAPUE) MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor DDRAx RESET PTAx Figure 12-4. Port A I/O Circuit Table 12-2 summarizes the operation of the port A pins. Table 12-2. Port A Pin Functions ...
Page 128
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 128 PTB6 PTB5 PTB4 Unaffected by reset AD6 AD5 AD4 Figure 12-6. Port B Data Register (PTB) NOTE DDRB6 DDRB5 DDRB4 DDRB3 Bit 0 PTB3 PTB2 PTB1 PTB0 AD3 AD2 AD1 AD0 2 1 Bit 0 DDRB2 DDRB1 DDRB0 Freescale Semiconductor ...
Page 129
... Writing affects data register, but does not affect input. 12.4 Port C Port 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NOTE DDRBx RESET PTBx Figure 12-8 ...
Page 130
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 130 NOTE PTC6 PTC5 PTC4 PTC3 Unaffected by reset Figure 12-9. Port C Data Register (PTC DDRC6 DDRC5 DDRC4 DDRC3 NOTE NOTE 2 1 Bit 0 PTC2 PTC1 PTC0 2 1 Bit 0 DDRC2 DDRC1 DDRC0 Freescale Semiconductor ...
Page 131
... PTCPUE6 Write: Reset Unimplemented Figure 12-12. Port C Input Pullup Enable Register (PTCPUE) MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor DDRCx RESET PTCx Figure 12-11. Port C I/O Circuit Table 12-4 summarizes the operation of the port C pins. Table 12-4. Port C Pin Functions ...
Page 132
... SPE, is clear, the SPI module is disabled, and the PTD0/SS pin is available for general-purpose I/O. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 132 PTD6 PTD5 PTD4 PTD3 Unaffected by reset T2CH0 T1CH1 T1CH0 SPSCK Chapter 18 Timer Interface Module Chapter 18 Timer Interface Module 2 1 Bit 0 PTD2 PTD1 PTD0 MOSI MISO SS (TIM). (TIM). Freescale Semiconductor ...
Page 133
... Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from Figure 12-15 shows the port D I/O logic. READ DDRD ($0007) WRITE DDRD ($0007) WRITE PTD ($0003) READ PTD ($0003) MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Table 12- DDRD6 DDRD5 ...
Page 134
... Accesses to DDRD I/O Pin Mode Read/Write (2) Input, V DDRD7–DDRD0 DD (4) Input, Hi-Z DDRD7–DDRD0 Output DDRD7–DDRD0 PTDPUE5 PTDPUE4 PTDPUE3 Accesses to PTD Read Write Pin PTD7–PTD0 Pin PTD7–PTD0 PTD7–PTD0 PTD7–PTD0 2 1 Bit 0 PTDPUE2 PTDPUE1 PTDPUE0 Freescale Semiconductor (3) (3) ...
Page 135
... Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing DDRE bit enables the output buffer for the corresponding port E pin disables the output buffer. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...
Page 136
... Figure 12-19. Port E I/O Circuit Table 12-6 summarizes the operation of the port E pins. Table 12-6. Port E Pin Functions Accesses to DDRE Read/Write (2) DDRE4–DDRE0 DDRE4–DDRE0 2 1 Bit 0 DDRE2 DDRE1 DDRE0 PTEx Accesses to PTE Read Write (3) Pin PTE4–PTE0 PTE4–PTE0 PTE4–PTE0 Freescale Semiconductor ...
Page 137
... All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin. See Figure 13-1. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor , generates an external reset. An external reset sets the IRL 137 ...
Page 138
... To clear the COP counter and prevent a COP reset, write any value to the COP control register at location $FFFF. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 138 PULLED LOW BY MCU 32 CYCLES Figure 13-1. Internal Reset Timing 4096 32 32 CYCLES CYCLES CYCLES Figure 13-2. Power-On Reset Recovery 32 CYCLES pin Freescale Semiconductor at the DD ...
Page 139
... Only a read of the SIM reset status register clears all reset flags. After multiple resets from different sources without reading the register, multiple flags remain set. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor TRIPR is below the LVI voltage and during the oscillator ...
Page 140
... Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other interrupt can take precedence, regardless of its priority. • Loads the program counter with a user-defined vector address MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 140 PIN COP ILOP ILAD Unimplemented 2 1 Bit 0 MODRST LVI Freescale Semiconductor ...
Page 141
... Figure 13- interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. INT1 INT2 Figure 13-5 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor • • • CONDITION CODE REGISTER 1 ACCUMULATOR ...
Page 142
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 142 YES BREAK ? NO NO YES IRQ ? NO YES ICG ? NO OTHER YES ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR SWI YES ? NO RTI YES UNSTACK CPU REGISTERS ? NO EXECUTE INSTRUCTION Figure 13-6. Interrupt Processing NOTE SET I BIT Freescale Semiconductor ...
Page 143
... ADC conversion complete Timebase 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction highest priority MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NOTE Table 13-1. Interrupt Sources INT Register (1) ...
Page 144
... The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control register. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 144 Freescale Semiconductor ...
Page 145
... When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Interrupts 145 ...
Page 146
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 146 Table 13-2. Interrupt Source Flags Interrupt Status Interrupt Source Table 13-2 summarizes the Register Flag — — IF1 IF2 IF3 IF4 IF5 IF6 IF7 IF8 IF9 IF10 IF11 IF12 IF13 IF14 IF15 IF16 Freescale Semiconductor ...
Page 147
... IF16–IF15 — Interrupt Flags 16–15 This flag indicates the presence of an interrupt request from the source shown Interrupt request present interrupt request present Bits 7–2 — Always read 0 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor IF5 ...
Page 148
... Resets and Interrupts MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 148 Freescale Semiconductor ...
Page 149
... ESCI I/O pins. The generic pin names appear in the text of this section. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Table 14-1 shows the full names and the generic names of the ...
Page 150
... PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1)(2) PTC4 (1)(2) PTC3 (1)(2) PTC2 (1)(2) PTC1 (1)(2) PTC0 PTD7/T2CH1 PTD6/T2CH0 PTD5/T1CH1 PTD4/T1CH0 PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE TxD PTE0/TxD Freescale Semiconductor (1) (1) (1) (1) (1) ...
Page 151
... RE TC RWU SCRF SBK IDLE WAKEUP CONTROL ENSCI PRE- PRE- ÷ 4 SCALER SCALER Figure 14-2. ESCI Module Block Diagram MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor INTERNAL BUS LOOPS LOOPS ENSCI RECEIVE FLAG CONTROL CONTROL M BKF WAKE ...
Page 152
... PARITY OR DATA NEXT BIT START BIT BIT 8 STOP BIT Bit 0 PSSB3 PSSB2 PSSB1 PSSB0 AFIN ARUN AROVFL ARD8 ARD3 ARD2 ARD1 ARD0 WAKE ILTY PEN RWU ORIE NEIE FEIE BKF SCR2 SCR1 SCR0 Reserved U = Unaffected Freescale Semiconductor PTY 0 SBK 0 PEIE RPF ...
Page 153
... During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin. The ESCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor INTERNAL BUS ÷ ...
Page 154
... For TXINV = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 154 Freescale Semiconductor ...
Page 155
... SCDR. The ESCI receiver full bit, SCRF, in ESCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the ESCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NOTE Functional Description 155 ...
Page 156
... INTERNAL BUS SCR1 SCR2 SCR0 BAUD ÷ 16 DIVIDER DATA H RECOVERY ALL ZEROS WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE OR ORIE NF NEIE FE FEIE PE PEIE ESCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER RWU SCRF IDLE R8 ILIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor ...
Page 157
... To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-3 summarizes the results of the data bit samples. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor START BIT START BIT START BIT DATA ...
Page 158
... Table 14-3. Data Bit Recovery Data Bit Determination 000 0 001 0 010 0 011 1 100 0 101 1 110 1 111 1 NOTE Table 14-4. Stop Bit Recovery Framing Error Flag 000 1 001 1 010 1 011 0 100 1 101 0 110 0 111 0 Noise Flag Table 14-4 Noise Flag Freescale Semiconductor ...
Page 159
... The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. RECEIVER RT CLOCK MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor MSB STOP DATA SAMPLES Figure 14-8. Slow Data ...
Page 160
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 160 Figure 14-9, the receiver counts 154 RT cycles at the point when 154 160 – × 100 = 3.90%. ------------------------- - 154 Figure 14-9, the receiver counts 170 RT cycles at the point when 170 176 – × 100 = 3.53%. ------------------------- - 170 NOTE Freescale Semiconductor ...
Page 161
... ESCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission or reception results in invalid data. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Low-Power Modes 161 ...
Page 162
... ESCI data register, SCDR • ESCI baud rate register, SCBR • ESCI prescaler register, SCPSC • ESCI arbiter control register, SCIACTL • ESCI arbiter data register, SCIADAT MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 162 Support. Freescale Semiconductor ...
Page 163
... This read/write bit determines whether ESCI characters are eight or nine bits long (See Table 14-5).The ninth bit can serve as a receiver wakeup signal parity bit. Reset clears the M bit 9-bit ESCI characters 0 = 8-bit ESCI characters MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ENSCI TXINV ...
Page 164
... None 1 7 Even 1 7 Odd 1 8 Even 1 8 Odd Table Table 14-3). Reset clears the PEN bit. NOTE Stop Bits Character Length 1 10 bits 1 11 bits 1 10 bits 1 10 bits 1 11 bits 1 11 bits 14-5). When enabled, the parity Freescale Semiconductor ...
Page 165
... This read/write bit enables the IDLE bit to generate ESCI receiver CPU interrupt requests. Reset clears the ILIE bit IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...
Page 166
... Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the ESCI to send a break character instead of a preamble. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 166 NOTE NOTE NOTE Freescale Semiconductor ...
Page 167
... This read/write bit enables ESCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE ESCI error CPU interrupt requests from PE bit enabled 0 = ESCI error CPU interrupt requests from PE bit disabled MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...
Page 168
... ESCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 168 SCRF IDLE Unimplemented 2 1 Bit Freescale Semiconductor ...
Page 169
... OR bit in a second read of SCS1 after reading the data register. BYTE 1 READ SCS1 READ SCDR BYTE 1 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NORMAL FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = 1 SCRF = 1 ...
Page 170
... Polling RPF before disabling the ESCI module or entering stop mode can show whether a reception is in progress Reception in progress reception in progress MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 170 Unimplemented 2 1 Bit 0 0 BKF RPF Freescale Semiconductor ...
Page 171
... LINR — LIN Receiver Bits This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol as shown in Table 14-6. Reset clears LINR. LINR MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Unaffected by reset NOTE ...
Page 172
... Table 14-7. ESCI Baud Rate Prescaling Baud Rate Register Prescaler Divisor (BPD) Table 14-8. ESCI Baud Rate Selection Baud Rate Divisor (BD) 128 NOTE PDS1 PDS0 PSSB4 PSSB3 Table 14-7. Reset Table 14-8. Reset clears Bit 0 PSSB2 PSSB1 PSSB0 Freescale Semiconductor ...
Page 173
... Table 14-10. ESCI Prescaler Divisor Fine Adjust PSSB[4:3:2:1: MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Table 14-9. Reset clears PDS2–PDS0. NOTE Prescaler Divisor (PD) Bypass this prescaler Table Prescaler Divisor Fine Adjust (PDFA) 0/ 1/32 = 0.03125 2/32 = 0.0625 3/ ...
Page 174
... Bus = ----------------------------------------------------------------------------------- - × × × BPD PDFA ) Freescale Semiconductor ...
Page 175
... Table 14-11. ESCI Baud Rate Selection Examples PS[2:1:0] PSSB[4:3:2:1: MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Prescaler SCP[1:0] Divisor SCR[2:1:0] (BPD I/O Registers Baud Rate Baud Rate Divisor (f = 4.9152 MHz) Bus (BD) 1 76,800 1 9600 1 9562.65 1 9525.58 1 8563.07 ...
Page 176
... Arbiter counter stopped MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 176 ALOST AFIN AM0 ACLK Unimplemented ESCI Arbiter Mode Idle / counter reset Bit time measurement Bus arbitration Reserved / do not use 2 1 Bit 0 ARUN AROVFL ARD8 Table 14-12. Reset clears Freescale Semiconductor ...
Page 177
... ALOST is set. As long as ALOST is set, the TxD pin is forced to 1, resulting in a seized transmission. If SCI_TxD is sensed 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration operation will be restarted after the next rising edge of SCI_TxD. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...
Page 178
... Figure 14-21. Bit Time Measurement with ACLK = 0 RXD Figure 14-22. Bit Time Measurement with ACLK = 1, Scenario A RXD Figure 14-23. Bit Time Measurement with ACLK = 1, Scenario B MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 178 MEASURED TIME MEASURED TIME MEASURED TIME Freescale Semiconductor ...
Page 179
... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Table 15-1. Signal Name Conventions Description 179 ...
Page 180
... CGMXCLK (FROM ICG) CGMOUT (FROM ICG) INTERNAL CLOCKS FORCED MONITOR MODE ENTRY LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE SBSW NOTE ILOP ILAD MODRST LVI Freescale Semiconductor Bit ...
Page 181
... ECLK CLOCK SELECT CIRCUIT ICLK ICG GENERATOR CS ICG 15.2.1 Bus Timing In user mode, the internal bus frequency is the internal clock generator output (CGMXCLK) divided by four. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Bit BCFE IF6 IF5 IF4 R R ...
Page 182
... CGMOUT RST IAB PC MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 182 15.6.2 Stop Mode. 15.4 SIM Counter), but an external reset does not. Each of shows the relative timing. VECT H VECT L Figure 15-4. External Reset Timing 15.7 SIM Registers. Freescale Semiconductor ...
Page 183
... The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor NOTE RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 15-5 ...
Page 184
... The SIM actively pulls down the RST pin for all internal reset sources. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 184 32 32 CYCLES CYCLES Figure 15-7. POR Recovery on the RST pin disables the COP module. TST $FFFE $FFFF while the MCU is in monitor TST Freescale Semiconductor ...
Page 185
... External reset has no effect on the SIM counter. See free-running after all reset states. See internal reset recovery sequences. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 15.6.2 Stop Mode 15.3.2 Active Resets from Internal Sources SIM Counter voltage falls to the DD 19 ...
Page 186
... SP – – – – Figure 15-8 Interrupt Entry Timing SP – – – – 1 [7:0] PC – 1 [15:8] OPCODE Figure 15-9. Interrupt Recovery Timing Figure 15-10. Figure 15-8 shows VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPERAND Freescale Semiconductor ...
Page 187
... If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 15-11 demonstrates what happens when two interrupts are pending interrupt MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor FROM RESET BREAK I BIT SET? YES ...
Page 188
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 188 NOTE CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE BACKGROUND ROUTINE Table 15-3 summarizes the Freescale Semiconductor ...
Page 189
... These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Bit 0 and Bit 1 — Always read 0 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Table 15-3. Interrupt Sources Interrupt Source Reset SWI instruction ...
Page 190
... SIM break flag control register (SBFCR). MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 190 I13 I12 I11 I10 Reserved Reserved 2 1 Bit Table 15- Bit 0 0 I16 I15 Table 15-3. (TIM)). The SIM puts the CPU into the Freescale Semiconductor ...
Page 191
... CONFIG1 register is 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Figure 15-16 and Figure 15-17 MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 15-15. Wait Mode Entry Timing show the timing for WAIT recovery ...
Page 192
... To minimize stop current, all pins configured as inputs should be driven MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 192 $6E0B $6E0C $00FF $00FE $A6 $A6 $01 $ CYCLES CYCLES $A6 NOTE Figure 15-18 NOTE $00FD $00FC $6E RST VCT H RST VCT L shows stop mode entry timing. Freescale Semiconductor ...
Page 193
... Write: Reset Note: 1. Writing a 0 clears SBSW. Figure 15-20. SIM Break Status Register (SBSR) MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor STOP ADDR + 1 PREVIOUS DATA NEXT OPCODE Figure 15-18. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 ...
Page 194
... POR while IRQ ≠ V TST 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 194 PIN COP ILOP ILAD Bit 0 MODRST LVI Freescale Semiconductor ...
Page 195
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor ...
Page 196
... System Integration Module (SIM) MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 196 Freescale Semiconductor ...
Page 197
... If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. The following paragraphs describe the operation of the SPI module. Refer to of the SPI I/O registers. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor Figure 16-2 for a summary 197 ...
Page 198
... PTA7/KBD7– (1) PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1)(2) PTC4 (1)(2) PTC3 (1)(2) PTC2 (1)(2) PTC1 (1)(2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 199
... Register (SPSCR) Write: See page 214. Reset: Read: SPI Data Register $0012 (SPDR) Write: See page 216. Reset: MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER SPR0 ...
Page 200
... MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 200 NOTE Figure 16-4. MISO MISO MOSI MOSI SPSCK SPSCK Register.) Through the SPSCK pin, the baud rate generator of the 16.12.1 SPI SLAVE MCU SHIFT REGISTER 16.6.2 Mode Fault Error. Freescale Semiconductor ...