COP8SAA720M8 National Semiconductor, COP8SAA720M8 Datasheet - Page 8

IC MCU OTP 8BIT 1K POR 20-SOIC

COP8SAA720M8

Manufacturer Part Number
COP8SAA720M8
Description
IC MCU OTP 8BIT 1K POR 20-SOIC
Manufacturer
National Semiconductor
Series
COP8™ 8SAr
Datasheet

Specifications of COP8SAA720M8

Core Processor
COP8
Core Size
8-Bit
Speed
10MHz
Connectivity
Microwire/Plus (SPI)
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1KB (1K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SAA720M8
www.national.com
Instruction Cycle Time (t
External CKI Clock Duty Cycle (Note 8)
Inputs
Output Propagation Delay (Note 7)
MICROWIRE Setup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t
MICROWIRE Maximum Shift Clock
Input Pulse Width (Note 7)
Reset Pulse Width
AC Electrical Characteristics
Note 2: t
Note 3: Maximum rate of voltage change must be
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of I
programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
biased at voltages
pins will not latch up. The voltage at the pins must be limited to
excludes ESD transients.
Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 8: Parameter characterized but not tested.
Note 9: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.
0˚C
Crystal/Resonator, External
Internal R/C Oscillator
R/C Oscillator Frequency Variation
(Note 8)
Rise Time (Note 8)
Fall Time (Note 8)
t
t
t
SO, SK
All Others
Master Mode
Slave Mode
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
SETUP
HOLD
PD1
, t
T
PD0
C
A
= Instruction cycle time (Clock input frequency divided by 10).
+70˚C unless otherwise specified.
>
V
Parameter
CC
(the pins do not have source current when biased at a voltage below V
C
)
UWH
UWS
) (Note 7)
) (Note 7)
<
UPD
0.5 V/ms.
)
DD
<
4.5V
2.7V
4.5V
2.7V
4.5V
2.7V
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
4.5V
2.7V
4.5V
2.7V
R
4.5V
2.7V
4.5V
2.7V
HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning
L
= 2.2k, C
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Conditions
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
8
<
<
<
<
<
<
<
L
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
4.5V
4.5V
4.5V
4.5V
4.5V
= 100 pF
4.5V
4.5V
CC
). The effective resistance to V
>
Min
200
500
150
1.0
2.0
45
60
20
56
V
1
1
1
1
1
CC
and the pins will have sink current to V
CC
; WATCHDOG and clock monitor disabled.
1.667
TBD
Typ
CC
is 750
TBD
Max
1.75
±
220
500
DC
DC
0.7
1.0
2.5
55
12
8
1
35
(typical). These two
CC
Units
MHz
kHz
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
µs
%
%
%
t
t
t
t
when
C
C
C
C
CC

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