MC68HC908BD48IFB Freescale Semiconductor, MC68HC908BD48IFB Datasheet

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MC68HC908BD48IFB

Manufacturer Part Number
MC68HC908BD48IFB
Description
IC MCU 48K FLASH 6MHZ USB 44PQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908BD48IFB

Core Processor
HC08
Core Size
8-Bit
Speed
6MHz
Connectivity
I²C, USB
Peripherals
POR, PWM
Number Of I /o
32
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 85°C
Package / Case
44-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908BD48IFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908BD48
Data Sheet
M68HC08
Microcontrollers
Rev. 2.1
MC68HC908BD48/D
August 1, 2005
freescale.com

Related parts for MC68HC908BD48IFB

MC68HC908BD48IFB Summary of contents

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MC68HC908BD48 Data Sheet M68HC08 Microcontrollers Rev. 2.1 MC68HC908BD48/D August 1, 2005 freescale.com ...

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...

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... To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor © Freescale, Inc., 2003 Data Sheet 3 ...

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... QFP drawing, case 824E to case 824A. Section 9. Monitor ROM (MON) Monitor Mode 8/1/2005 2.1 Updated to meet Freescale identity guidelines. Data Sheet 4 Revision History Description — Timer — Replaced incorrect — Updated Figure 9-1 . Circuit. Page Number(s) 125 283 117 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... Section 17. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 229 Section 18. External Interrupt (IRQ 251 Section 19. Computer Operating Properly (COP 257 Section 20. Break Module (BRK 263 Section 21. Electrical Specifications 271 Section 22. Mechanical Specifications . . . . . . . . . . . . . 283 Section 23. Ordering Information . . . . . . . . . . . . . . . . . 285 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor List of Sections List of Sections Data Sheet 5 ...

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... List of Sections Data Sheet 6 MC68HC908BD48 List of Sections Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Section 2. Memory Map Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 35 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Input/Output (I/O) Section Section 3 ...

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... Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table of Contents MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Instruction Set Summary Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Section 7. System Integration Module (SIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 91 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 91 Reset and System Initialization ...

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... Oscillator During Break Mode 114 Section 9. Monitor ROM (MON) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Table of Contents MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... TIM Channel Registers (TCH0H/L:TCH1H/ 145 11.1 11.2 11.3 11.4 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 10. Timer Interface Module (TIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Output Compare ...

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... ADC Status and Control Register .158 ADC Data Register 160 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 161 Section 13. Universal Serial Bus Module (USB) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Registers .165 USB Address Register (UADR 166 Table of Contents MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor USB Interrupt Register (UINTR 166 USB Interrupt Register 1 (UIR1 169 USB Control Register 0 (UCR0 171 USB Control Register 1 (UCR1 172 USB Control Register 2 (UCR2 174 USB Status Register (USR 175 USB Endpoint 0 Data Registers (UD0R0– ...

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... Sync Processor Input/Output Control Register (SPIOCR) . 219 Vertical Frequency Registers (VFRs 221 Hsync Frequency Registers (HFRs 223 Sync Processor Control Register 1 (SPCR1 225 H&V Sync Output Control Register (HVOCR 226 System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Table of Contents MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 17. Input/Output (I/O) Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Port 233 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Data Direction Register 234 Port A Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Port 236 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Data Direction Register 237 Port B Options ...

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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 266 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .266 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 266 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 266 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Table of Contents MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... DDC12AB/MMIIC Interface Output Signal Timing . . . . . . . 279 21.14 Sync Processor Timing 280 21.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Break Status and Control Register 267 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 268 SIM Break Status Register ...

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... Data Sheet 18 Section 22. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 42-Pin Shrink Dual in-Line Package (SDIP 283 44-Pin Plastic Quad Flat Pack (QFP 284 Section 23. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Table of Contents MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 100 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Title MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 29 42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .39 FLASH Control Register (FLCR FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 60 FLASH Block Protect Register (FLBPR) ...

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... USB Address Register (UADR .166 13-2 USB Interrupt Register (UINTR 166 Data Sheet 20 Title Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . .112 Monitor Mode Circuit 117 Monitor Data Format 119 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Break Transaction .120 List of Figures Page MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... Hsync Frequency High Register . . . . . . . . . . . . . . . . . . . . . . . 223 16-8 Hsync Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . .223 16-9 Sync Processor Control Register 1 (SPCR1 225 16-10 H&V Sync Output Control Register (HVOCR 226 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Title Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 207 List of Figures List of Figures Page ...

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... SIM Break Status Register (SBSR 269 20-6 SIM Break Flag Control Register (SBFCR 270 21-1 ADC Input Voltage vs. Step Readings . . . . . . . . . . . . . . . . . . 277 22-2 42-Pin SDIP (Case #858 283 22-3 44-Pin QFP (Case #824A 284 Data Sheet 22 Title MC68HC908BD48 List of Figures Page Rev. 2.1 — Freescale Semiconductor ...

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... Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 144 11-1 PWM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 148 11-2 PWM Channels and Port I/O pins 151 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Title Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SIM I/O Register Summary .90 Signal Name Conventions ...

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... Port C Pin Functions 241 17-6 Port D Pin Functions 244 17-7 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 18-1 IRQ I/O Register Summary .253 20-1 Break Module I/O Register Summary . . . . . . . . . . . . . . . . . . . 265 23-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Data Sheet 24 Title MC68HC908BD48 List of Tables Page Rev. 2.1 — Freescale Semiconductor ...

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... Features Features of the MC68HC908BD48 MCU include the following: • • MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and ...

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... DDC is a VESA bus standard. 2. IIC is a proprietary Philips interface bus. Data Sheet 26 sync or composite sync inputs 1 module with the following: 2 hardware for DDC2AB; with dual address General Description MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... No security feature is absolutely secure. However, Freescale Freescale ’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor System protection features: – Optional computer operating properly (COP) reset – Illegal opcode detection with reset – Illegal address detection with reset ...

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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 80 BYTES USER FLASH — 48,128 BYTES USER RAM — 1024 BYTES MONITOR ROM — 512+470 BYTES USER FLASH VECTOR SPACE — 26 BYTES ‡ OSC1 OSCILLATOR ‡ ...

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... Pin Assignments PTE0/SOG/TCH0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor OSC2 1 OSC1 2 VSS 3 RST 4 PTB7/PWM7 5 PTB6/PWM6 6 PTB5/PWM5 7 PTC5/ADC5 8 PTC4/ADC4 9 IRQ 10 11 Figure 1-2. 44-Pin QFP Pin Assignments General Description General Description PTE2/VSYNCO 33 PTE1/HSYNCO 32 PTB0/PWM0 31 PTB1/PWM1 30 PTB2/PWM2 29 PTB3/PWM3 28 PTB4/PWM4 27 VSS1 PTD2/DDCSDA 24 PTD3/DDCSCL ...

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... PTA7/PWM15 17 PTA6/PWM14 18 PTA5/PWM13 19 PTA4/PWM12 20 PTA3/PWM11 21 Figure 1-3. 42-Pin SDIP Pin Assignments General Description 42 HSYNC 41 PTC0/ADC0 40 PTC1/ADC1 39 PTC2/ADC2 38 PTC3/ADC3 37 PTE2/VSYNCO 36 PTE1/HSYNCO 35 PTB0/PWM0 34 PTB1/PWM1 33 PTB2/PWM2 PTB3/PWM3 32 PTB4/PWM4 31 30 VSS1 29 PTD2/DDCSDA 28 PTD3/DDCSCL 27 PTD4/CLAMP 26 PTD5/IICSCL 25 PTD6/IICSDA 24 PTA0/PWM8 23 PTA1/PWM9 22 PTA2/PWM10 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... Pin Functions Description of the pin functions are provided in PTA7/PWM15–PTA0/PWM8 PTB7/PWM7–PTB0/PWM0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Table 1-1. Pin Functions PIN NAME VDD Power supply input to the MCU. VSS Power supply ground. VDD3 3.3V regulated output from the MCU. ...

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... PTD1/D– interface differential data lines. PTD0/D+ See Section 17. Input/Output (I/O) Ports Section 13. Universal Serial Bus Module General Description PIN DESCRIPTION and (ADC). and (MMIIC). and (MMIIC). and Processor. and Interface. and Interface. and (USB). MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... V MC68HC908BD48 do not require termination, termination is recommended to reduce the possibility of static damage. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Table 1-1. Pin Functions PIN NAME This is a shared function pin. It can be configured as a standard I/O pin or the Hsync output from the PTE2/VSYNCO sync processor ...

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... General Description Data Sheet 34 General Description MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. In the memory map (Figure locations are shaded. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 35 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Input/Output (I/O) Section Figure 2-1, includes: ...

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... Break Address Register Low, BRKL • $FE0E; Break Status and Control Register, BRKSCR Data registers are shown in locations. Data Sheet 36 Figure 2-1 and in register figures in this document, Figure 2-2. Table 2-1 MC68HC908BD48 Memory Map is a list of vector Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $0000 I/O Registers ↓ $005F $0060 Unimplemented ↓ $007F $0080 ↓ 1,024 Bytes $047F $0480 Unimplemented ↓ 1,920 Bytes $0BFF $0C00 ↓ 256 Bytes $0CFF $0D00 Unimplemented ↓ 13,056 Bytes $3FFF $4000 FLASH Memory ↓ ...

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... Break Address Register Low (BRKL) $FE0E Break Status and Control Register (BRKSCR) $FE0F Reserved $FE10 Monitor ROM ↓ 470 Bytes $FFE5 $FFE6 FLASH Vectors ↓ 26 Bytes $FFFF Figure 2-1. Memory Map (Continued) Memory Map MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... Port E Data Register $0008 Write: (PTE) Reset: Read: Data Direction Register E $0009 Write: (DDRE) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 12) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 Unaffected by reset ...

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... PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX Reserved MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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... Write: (D2ADR) Reset: Read: Configuration Register 0 $001D Write: (CONFIG0) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 12) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Bit Bit15 Bit14 Bit13 Bit12 Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Indeterminate after reset ...

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... STOP COPD 0PWM0 0BRM2 0BRM1 0BRM0 1PWM0 1BRM2 1BRM1 1BRM0 2PWM0 2BRM2 2BRM1 2BRM0 3PWM0 3BRM2 3BRM1 3BRM0 4PWM0 4BRM2 4BRM1 4BRM0 5PWM0 5BRM2 5BRM1 5BRM0 6PWM0 6BRM2 6BRM1 6BRM0 7PWM0 7BRM2 7BRM1 7BRM0 Reserved MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 43

... Read: UE0RD17 UE0RD16 UE0RD15 UE0RD14 UE0RD13 UE0RD12 UE0RD11 UE0RD10 USB Endpoint 0 Data $0031 Write: UE0TD17 UE0TD16 UE0TD15 UE0TD14 UE0TD13 UE0TD12 UE0TD11 UE0TD10 Register 1 (UD0R1) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 12) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Bit PWM7E PWM6E PWM5E PWM4E 0 0 ...

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... Indeterminate after reset Indeterminate after reset Indeterminate after reset Indeterminate after reset Indeterminate after reset Indeterminate after reset Indeterminate after reset Indeterminate after reset Indeterminate after reset Indeterminate after reset = Unimplemented Memory Map Bit Reserved MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 45

... Read: VSYNCS HSYNCS Sync Processor I/O $0045 Control Register Write: (SPIOCR) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 12) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Bit Indeterminate after reset Indeterminate after reset Indeterminate after reset Indeterminate after reset VSIF VSIE ...

Page 46

... MMRD4 Unimplemented Memory Map Bit ATPOL FSHF HVOCR2 HVOCR1 HVOCR0 USBD–E USBD+E DDCSCLE DDCDATE MMRW MMBR2 MMBR1 MMBR0 MMAD3 MMAD2 MMAD1 MMEXTAD MMTXAK MMTXBE MMRXBF MMTD3 MMTD2 MMTD1 MMTD0 MMRD3 MMRD2 MMRD1 MMRD0 Reserved MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 47

... Reset: Read: PWM15 Data Register $0058 Write: (15PWM) Reset: Read: PWM Control Register 2 $0059 Write: (PWMCR2) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 12) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Bit 8PWM4 8PWM3 8PWM2 8PWM1 9PWM4 9PWM3 9PWM2 9PWM1 0 0 ...

Page 48

... COCO AIEN ADCO ADCH4 AD7 AD6 AD5 AD4 Unaffected after Reset 0 ADIV2 ADIV1 ADIV0 POR PIN COP ILOP Unimplemented Memory Map Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 SBSW Note ILAD Reserved MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 49

... Reset: Read: $FE0A Reserved Write: Reset: Read: $FE0B Reserved Write: Reset: Read: Break Address High $FE0C Write: Register (BRKH) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 12) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Bit BCFE IF6 IF5 IF4 IF3 ...

Page 50

... Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 12) Data Sheet 50 Bit Bit7 Bit6 Bit5 Bit4 BRKE BRKA Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented Memory Map Bit 0 Bit3 Bit2 Bit1 Bit0 Reserved MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 51

... Vector Priority MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Table 2-1. Vector Addresses INT Flag Address Lowest $FFE6 — $FFE7 $FFE8 IF10 $FFE9 $FFEA IF9 $FFEB $FFEC IF8 $FFED $FFEE IF7 $FFEF $FFF0 IF6 $FFF1 $FFF2 IF5 $FFF3 $FFF4 IF4 $FFF5 $FFF6 ...

Page 52

... Memory Map Data Sheet 52 MC68HC908BD48 Memory Map Rev. 2.1 — Freescale Semiconductor ...

Page 53

... RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Random-Access Memory (RAM) Data Sheet 53 ...

Page 54

... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Data Sheet 54 Random-Access Memory (RAM) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 55

... The FLASH memory can be read, programmed, and erased from a single external supply through the use of the internal charge pump for program and erase. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 4. FLASH Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 FLASH Control Register (FLCR FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 57 FLASH Mass Erase Operation ...

Page 56

... FLASH Control Register (FLCR) The FLASH control register (FLCR) controls FLASH program and erase operations. Address: Read: Write: Reset: Data Sheet 56 $FE07 Bit Unimplemented Figure 4-1. FLASH Control Register (FLCR) FLASH Memory Bit 0 HVEN MASS ERASE PGM MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 57

... Write any data to any FLASH address within the block address 3. Wait for a time, t MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = High voltage enabled to array and charge pump High voltage disabled to array and charge pump off 1 = Mass Erase operation selected 0 = Mass Erase operation not selected ...

Page 58

... Data Sheet 58 (min. 2ms) Erase (min. 5µs) nvh (min. 1µs), the memory can be accessed again in rcv (5µs). nvs (4ms). MErase (100µs). nvhl (1µs) the memory can be accessed again in read rcv , MC68HC908BD48 FLASH Memory Rev. 2.1 — Freescale Semiconductor ...

Page 59

... FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed t Memory Characteristics. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor (Figure 4-2 operation and enables the latching of address and data for programming. range desired. (min. 5µs). nvs (min. 10µ ...

Page 60

... Wait for a time, t pgs 6 Write data to the FLASH address to be programmed 7 Wait for a time, t PROG Completed Y programming this row FLASH Memory Clear PGM bit Wait for a time, t nvh Clear HVEN bit Wait for a time, t rcv End of programming MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 61

... Bits [8:0] are logic 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $FE08 Bit BPR7 ...

Page 62

... Note: The user FLASH vectors from $FFE6 to $FFFF are always protected, and can only be erased by a FLASH mass erase operation. FLASH Memory 16-bit memory address MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 63

... All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU recommended that these registers be written immediately after reset. The configuration MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Configuration Register .64 Configuration Register .65 Sync Processor HSYNCO output pin ...

Page 64

... Data Sheet 64 $001D Bit SOGE Unimplemented Figure 5-1. Configuration Register 0 (CONFIG0) TCH0 function is configured by ELS0B and ELS0A bits in TSC0 (bits 3 and 2 in $0010). (See Status and Control Registers Configuration Register (CONFIG Bit 10.10.4 TIM Channel (TSC0:TSC1).) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 65

... COPRS selects the COP timeout period. Reset clears COPRS. Section 19. Computer Operating Properly STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. COPD — COP Disable Bit COPD disables the COP module. Operating Properly MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $001F Bit ...

Page 66

... Configuration Register (CONFIG) Data Sheet 66 Configuration Register (CONFIG) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 67

... M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Stack Pointer ...

Page 68

... Kbytes • Low-power stop and wait modes 6.4 CPU Registers Figure 6-1 the memory map. Data Sheet 68 shows the five CPU registers. CPU registers are not part of Central Processor Unit (CPU) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 69

... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Figure 6-1. CPU Registers Bit Unaffected by reset Figure 6-2. Accumulator (A) Central Processor Unit (CPU) ...

Page 70

... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Data Sheet 70 Bit Indeterminate Figure 6-3. Index Register (H:X) Central Processor Unit (CPU) Bit MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 71

... Read: Write: Reset: 6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Bit ...

Page 72

... The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Data Sheet 72 Bit Indeterminate Figure 6-6. Condition Code Register (CCR) Central Processor Unit (CPU Bit MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 73

... Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result Central Processor Unit (CPU) ...

Page 74

... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock Data Sheet 74 Central Processor Unit (CPU) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 75

... Opcode Map See MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock ...

Page 76

... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 77

... BMS rel Branch if Interrupt Mask Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? = (N ⊕ ← (PC rel ? ( ⊕ ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← ...

Page 78

... DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 79

... Decrement DEC opr,X DEC ,X DEC opr,SP DIV Divide MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Description (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – (M (X) – ...

Page 80

... FD 4 IMM DIR EXT IX2 – IX1 SP1 9EE6 ff 4 SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 81

... Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← ...

Page 82

... SP1 9E66 INH IMM DIR EXT IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 83

... TSX Transfer SP to H:X TXA Transfer TXS Transfer H MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Description A ← (A) – (M) PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...

Page 84

... Zero bit & Logical AND | Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) # Immediate value « Sign extend ← Loaded with ? If : Concatenated with Set or cleared — Not affected Central Processor Unit (CPU) CCR MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 85

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...

Page 86

... Central Processor Unit (CPU) Data Sheet 86 Central Processor Unit (CPU) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 87

... MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 91 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 91 Reset and System Initialization External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 93 Power-On Reset ...

Page 88

... SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SIM Break Status Register (SBSR 108 SIM Reset Status Register (SRSR 109 SIM Break Flag Control Register (SBFCR 110 7-1. Table 7-1 shows a summary of the SIM I/O registers. The System Integration Module (SIM) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 89

... RESET PIN LOGIC SIM RESET STATUS REGISTER MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET RESET PIN CONTROL CONTROL RESET INTERRUPT CONTROL AND PRIORITY DECODE Figure 7-1. SIM Block Diagram ...

Page 90

... OSCXCLK divided by four) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal System Integration Module (SIM Bit 0 SBSW Note ILAD IF2 IF1 IF10 IF9 IF8 IF7 Reserved MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 91

... OSCXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 OSCXCLK cycles. (See Mode.) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor OSCXCLK OSCOUT ÷ 2 OSCILLATOR OSC2 Figure 7-2. OSC Clock Signals ...

Page 92

... SIM (see Table 7-3. PIN Bit Set Table 7-3. PIN Bit Set Timing Number of Cycles Required to Set PIN POR 4163 (4096 + System Integration Module (SIM) (see 7.5 SIM Counter), but an Registers). Timing). Figure 7 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 93

... The internal reset signal then follows the sequence from the falling edge of RST shown in OSCXCLK The COP reset is asynchronous to the bus clock. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor RST IAB PC Figure 7-3. External Reset Timing Timing). An internal reset can be caused by an illegal Reset). Note that for POR resets, the SIM cycles through Figure 7-4 ...

Page 94

... The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. Data Sheet 94 ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR Figure 7-5. Sources of Internal Reset System Integration Module (SIM) INTERNAL RESET MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 95

... RST pin or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, V RST pin disables the COP module. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor OSC1 4096 32 CYCLES CYCLES RST IAB Figure 7-6 ...

Page 96

... The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine. Data Sheet 96 System Integration Module (SIM) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 97

... Normally, sequential program execution can be changed in three different ways: • • • MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor for counter control and internal reset Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) Reset Break interrupts System Integration Module (SIM) System Integration Module (SIM) (see 7 ...

Page 98

... SP – 4 VECT CCR . Figure 7-7 Interrupt Entry SP – – – 1[7:0] PC – 1[15:8] Figure 7-8. Interrupt Recovery System Integration Module (SIM) flow charts the handling of Figure VECT L START ADDR V DATA H V DATA L OPCODE OPCODE OPERAND MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 99

... YES (As many interrupts as exist on chip) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO IRQ YES INTERRUPT? NO USB YES INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? NO Figure 7-9. Interrupt Processing ...

Page 100

... Data Sheet 100 Processing.) CLI LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Figure 7-10 Interrupt Recognition Example System Integration Module (SIM) Figure Figure 7-10 BACKGROUND ROUTINE MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 101

... The interrupt status registers can be useful for debugging. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Table 7-4 summarizes the interrupt sources and the interrupt System Integration Module (SIM) System Integration Module (SIM) Data Sheet 101 ...

Page 102

... MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 103

... Interrupt Status Register 2 Address: Read: Write: Reset: IF10–IF7 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Bit 7 and Bit 4 — Always read 0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $FE04 Bit IF6 IF5 IF4 ...

Page 104

... Upon leaving break mode, execution of the second step will clear the flag as normal. Data Sheet 104 (BRK)). The SIM puts the CPU into the System Integration Module (SIM) (see MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 105

... Figure 7-14 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Figure 7-13 shows the timing for wait mode entry. IAB WAIT ADDR WAIT ADDR + 1 IDB ...

Page 106

... IDB $A6 $A6 $A6 $01 Figure 7-14. Wait Recovery from Interrupt or Break 32 Cycles $6E0B $A6 $A6 $A6 Figure 7-15. Wait Recovery from Internal Reset System Integration Module (SIM) $00FF $00FE $00FD $00FC $0B $6E 32 Cycles RST VCT H RST VCT L MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 107

... NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. OSCXCLK INT/BREAK IAB Figure 7-17. Stop Mode Recovery from Interrupt or Break MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Figure 7-16 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA R/W Figure 7-16 ...

Page 108

... Table 7-5. SIM Registers Summary Address Register $FE00 SBSR $FE01 SRSR $FE03 SBFCR $FE00 Bit Reserved Figure 7-18. SIM Break Status Register (SBSR) System Integration Module (SIM) Table 7-5 shows the Access Mode User User User Bit 0 SBSW Note MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 109

... POR bit and clears all other bits in the register. Address: Read: Write: POR: POR — Power-On Reset Bit MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ...

Page 110

... MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Data Sheet 110 $FE03 Bit BCFE Reserved System Integration Module (SIM Bit MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 111

... SIM for bus clock generation. shows the structure of the oscillator. The oscillator requires various external components. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 8. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . .112 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Crystal Amplifier Input Pin (OSC1 113 Crystal Amplifier Output Pin (OSC2) ...

Page 112

... Pierce S To SIM OSCXCLK OSC1 OSC2 Figure 8-1. Oscillator External Connections Oscillator (OSC) 8-1. This figure shows only To SIM OSCOUT ÷ can be zero (shorted) when used with S higher-frequency crystals. Refer to manufacturer’s data. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 113

... SIM and results in the internal bus frequency being one fourth of the OSCXCLK frequency. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ) and comes directly from the crystal oscillator circuit. XCLK shows only the logical relation of OSCXCLK to OSC1 and Oscillator (OSC) Oscillator (OSC) ...

Page 114

... SIM module. 8.5.2 Stop Mode The STOP instruction disables the OSCXCLK output. 8.6 Oscillator During Break Mode The oscillator continues drive OSCXCLK when the chip enters the break state. Data Sheet 114 MC68HC908BD48 Oscillator (OSC) Rev. 2.1 — Freescale Semiconductor ...

Page 115

... This section describes the monitor ROM. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 9. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Data Format ...

Page 116

... MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pull-up resistor. Data Sheet 116 Figure 9-1 shows a sample circuit used to enter monitor Monitor ROM (MON) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 117

... GND C2 µF 6 V– 5 C2– DB9 NOTES: Position A — Bus clock = OSCXCLK ÷ 4 Position B — Bus clock = OSCXCLK ÷ 2 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor µF 1 µ TST µ 74HC125 5 6 74HC125 Figure 9-1. Monitor Mode Circuit Monitor ROM (MON) ...

Page 118

... ROM firmware. Data Sheet 118 shows the pin conditions for entering monitor mode. Table 9-1. Mode Selection Mode Monitor Monitor Monitor ROM (MON) Bus OSCOUT Frequency OSCXCLK OSCXCLK --------------------------- - --------------------------- - 4 2 OSCXCLK --------------------------- - OSCXCLK 2 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 119

... Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See START BREAK MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor for more information on modes of operation summary of the differences between user mode and Table 9-2. Mode Differences Modes COP Vector User ...

Page 120

... ROM immediately echoes each READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW Figure 9-4. Read Transaction MISSING STOP BIT Figure 9-5. Break Transaction Monitor ROM (MON) DATA RESULT Figure 9-5). TWO-STOP-BIT DELAY BEFORE ZERO ECHO MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 121

... Description MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program) Table 9-3. READ (Read Memory) Command Read byte from memory ...

Page 122

... Read Next 2 Bytes in Memory from Last Address Accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence SENT TO MONITOR IREAD IREAD ECHO Monitor ROM (MON) DATA DATA LOW DATA DATA RETURN MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 123

... A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-kbyte memory map. Description Operand Returned MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Table 9-6. IWRITE (Indexed Write) Command Write to last address accessed + 1 Specifies single data byte Data None Opcode $19 ...

Page 124

... Command Sequence SENT TO MONITOR RUN RUN ECHO Table 9-9. Monitor Baud Rate Selection Crystal Frequency PTC3 Pin 19.66 MHz 0 9.83 MHz 0 9.83 MHz 1 Monitor ROM (MON) Baud Rate 19200 bps 9600 bps 4800 bps MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 125

... TIM Counter Modulo Registers (TMODH:TMODL 140 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) . 141 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/ 145 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 10. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 TIM Counter Prescaler ...

Page 126

... TIM Generic Pin Names: Full TIM Pin Names: Data Sheet 126 Table 10-1. The generic pin name appear in the Table 10-1. Pin Name Conventions TCH0 PTE0/SOG/TCH0 Timer Interface Module (TIM) Figure TCH1 Not Available MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 127

... COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor shows the structure of the TIM. The central component of PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A ...

Page 128

... PS2 PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 129

... When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Read: Bit15 Bit14 Bit13 Write: Reset: ...

Page 130

... Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. Data Sheet 130 10.5.3 Output Compare. The pulses are Timer Interface Module (TIM) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 131

... Program the TIM to set the pin if the state of the PWM pulse is logic zero. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Figure 10-2 shows, the output compare value in the TIM channel Timer Interface Module (TIM) Timer Interface Module (TIM) Data Sheet ...

Page 132

... PULSE WIDTH OUTPUT COMPARE COMPARE Figure 10-2. PWM Period and Pulse Width 10.10.1 TIM Status and Control Register 10.5.4 Pulse Width Modulation Timer Interface Module (TIM) OVERFLOW OUTPUT OUTPUT COMPARE (TSC)). (PWM). The pulses are MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 133

... I/O pin. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value ...

Page 134

... Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Timer Interface Module (TIM) Table 10-4.) Table 10-4.) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 135

... TIM before executing the WAIT instruction. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor (TSC0:TSC1). TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests ...

Page 136

... TCH0 pin is programmable independently as an input capture pin or an output compare pin. It also can be configured as a buffered output compare or buffered PWM pin. Data Sheet 136 7.8.3 SIM Break Flag Control Register Timer Interface Module (TIM) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 137

... TIM status and control register when TOF is set and then writing a logic zero to TOF. If another TIM overflow occurs before the MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) ...

Page 138

... PS[2:0] — Prescaler Select Bits These read/write bits select either the TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as shows. Reset clears the PS[2:0] bits. Data Sheet 138 Timer Interface Module (TIM) Table 10-3 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 139

... TIM counter registers. NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Table 10-3. Prescaler Selection PS1 PS0 ...

Page 140

... TCNTH Bit Bit15 Bit14 Bit13 Bit12 $000D TCNTL Bit Bit7 Bit6 Bit5 Bit4 Unimplemented Figure 10-4. TIM Counter Registers (TCNTH:TCNTL) Timer Interface Module (TIM Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 141

... TIM Channel Status and Control Registers (TSC0:TSC1) Each of the TIM channel status and control registers does the following: • • • • • • • • MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $000E TMODH Bit Bit15 Bit14 Bit13 $000F TMODL ...

Page 142

... Channel x CPU interrupt requests disabled Data Sheet 142 $0010 TSC0 Bit CH0F CH0IE MS0B MS0A $0013 TSC1 Bit CH1F 0 CH1IE MS1A Unimplemented Timer Interface Module (TIM Bit 0 ELS0B ELS0A TOV0 CH0MAX Bit 0 ELS1B ELS1A TOV1 CH1MAX MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 143

... I/O port , and pin TCHx is available as a general-purpose port I/O pin. the ELSxB and ELSxA bits. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled Table 10- Unbuffered output compare/PWM operation 0 = Input capture operation (See Table 10-4 ...

Page 144

... Pin under Port Control; Initial Output Level Low Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 145

... TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor OVERFLOW OVERFLOW OVERFLOW PERIOD OUTPUT OUTPUT COMPARE COMPARE Figure 10-7 ...

Page 146

... Indeterminate after reset $0015 TCH1L Bit Bit7 Bit6 Bit5 Bit4 Indeterminate after reset Timer Interface Module (TIM Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 147

... The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. Examples of the waveforms are shown in MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 PWM Registers 149 PWM Data Registers (0PWM–15PWM 150 PWM Control Registers 1 and 2 (PWMCR1:PWMCR2 151 ...

Page 148

... PWM3E PWM2E PWM1E PWM0E MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 149

... Write: (PWMCR2) Reset: 11.4 PWM Registers The PWM module uses of 18 registers for data and control functions. • • MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 8PWM4 8PWM3 8PWM2 8PWM1 9PWM4 9PWM3 9PWM2 9PWM1 10PWM4 10PWM3 10PWM2 10PWM1 10PWM0 10BRM2 11PWM4 11PWM3 11PWM2 11PWM1 11PWM0 11BRM2 ...

Page 150

... Examples of PWM output waveforms are shown in Data Sheet 150 $0020–$0027 and $0051–$0058 Bit xPWM4 xPWM3 xPWM2 xPWM1 Pulse Width Modulator (PWM Bit 0 xPWM0 xBRM2 xBRM1 xBRM0 ÷ 32. OP Figure 11-3. Figure 11-3. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 151

... Setting a bit to 1 will enable the corresponding PWM channel to use as PWM output. A zero configures the corresponding PWM pin as a standard I/O port pin. Reset clears these bits. Port Pin MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor PWM7E PWM6E PWM5E PWM15E PWM14E PWM13E PWM12E PWM11E PWM10E 0 0 ...

Page 152

... PWM cycle = 32T 31T 16T 31T Pulse inserted at end of PWM cycle depends on setting of N. PWM cycles where pulses are Number of inserted pulses inserted in a 8-cycle frame in a 8-cycle frame Pulse Width Modulator (PWM) 16T MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 153

... Introduction This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit 6-channels analog-to-digital converter. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Continuous Conversion ...

Page 154

... Bit COCO AIEN ADCO ADCH4 AD7 AD6 AD5 AD4 Indeterminate after Reset 0 ADIV2 ADIV1 ADIV0 Unimplemented Figure 12-1 Analog-to-Digital Converter (ADC Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 shows a block diagram of the MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 155

... ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor DDRCx RESET PTCx ADC DATA REGISTER ADC VOLTAGE IN ...

Page 156

... ADC status and control register or reading of the ADC data register. Data Sheet 156 2 V and $00 if less than V ------ - ADC Clock Cycles Conversion Time = ADC Clock Frequency Analog-to-Digital Converter (ADC the ADC converts the ------ - the ADC and V are a ------ - MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 157

... MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode. 12.7 I/O Signals The ADC module has 6 channels that are shared with I/O port C. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC) Data Sheet 157 ...

Page 158

... When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always be logic 0 when read. Data Sheet 158 $005D Bit COCO AIEN ADCO ADCH4 Unimplemented Analog-to-Digital Converter (ADC Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 159

... MCU when the ADC is not used. Reset sets all of these bits to a logic 1. NOTE: Recovery from the disabled state requires one conversion cycle to stabilize. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = ADC interrupt enabled 0 = ADC interrupt disabled 1 = Continuous ADC conversion 0 = One ADC conversion Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC) Table 12-2 ...

Page 160

... Input Select ADC0 PTC0 ADC1 PTC1 ADC2 PTC2 ADC3 PTC3 ADC4 PTC4 ADC5 PTC5 Unused — (see Note 1) — Reserved — Unused V (see Note 2) DDA V (see Note 2) SSA ADC power off Bit 0 AD3 AD2 AD1 AD0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 161

... ADC to generate the internal ADC clock. shows the available clock configurations. The ADC clock should be set to approximately 1MHz. With an internal bus frequency of 6MHz, set ADIV[2:0] = 010, for a divide by four ADC clock rate don’t care MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $005F Bit ADIV2 ADIV1 ADIV0 ...

Page 162

... Analog-to-Digital Converter (ADC) Data Sheet 162 Analog-to-Digital Converter (ADC) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 163

... Endpoint 0 functions as a receive/transmit control endpoint. Endpoints 1 and 2 can function as interrupt or bulk, but only in transmit direction. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Registers .165 USB Address Register (UADR 166 USB Interrupt Register (UINTR 166 USB Interrupt Register 1 (UIR1) ...

Page 164

... D+ D– Data Sheet 164 Full MCU Pin Names: PTD0/D+ USBD+E bit in PDCR ($0049) PTD1/D– USBD–E bit in PDCR ($0049) Universal Serial Bus Module (USB) Table 13-1. The generic Pin Selected for USB Function By: MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 165

... Write: UE1TDx7 UE1TDx6 UE1TDx5 UE1TDx4 UE1TDx3 UE1TDx2 UE1TDx1 UE1TDx0 $003F (UD1R0–UD1R7) Reset: 13.5 Registers There are seven control/status registers and 24 data buffers in the USB module. These registers are discussed in the following paragraphs. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Table 13-2. USB I/O Register Summary Bit USBEN UADD6 UADD5 0 0 ...

Page 166

... Figure 13-1. USB Address Register (UADR) $002A Bit TBEF RBFF EOPIF RSTIF Unimplemented Figure 13-2. USB Interrupt Register (UINTR) Universal Serial Bus Module (USB Bit 0 UADD3 UADD2 UADD1 UADD0 Bit 0 TBIE RBIE EORIE RSTIE MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 167

... RSTIF generates an interrupt request to the CPU if the RSTIE bit is also set. Reset clears this bit. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = Transmit on endpoint 0 has occurred 0 = Transmit on endpoint 0 has not occurred 1 = Receive on endpoint 0 has occurred 0 = Receive on endpoint 0 has not occurred 1 = End-of-packet sequence has been detected ...

Page 168

... Since there are more than one interrupt flags in the register possible that program use Read-Modify-Write instruction to clear one flag, will occasionally clear the other flags which was just set after Read cycle of Read-Modify-Write operation. Data Sheet 168 Universal Serial Bus Module (USB) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 169

... USB reset signals cannot be detected while in suspend mode until SUSPND bit is cleared. The RESUMF interrupt service routine is generated by SE0 to wake up the USB module. This bit can be cleared by writing "1" to RESUMFR bit. Reset clears this bit. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $002E Bit TXD1F RESUMF ...

Page 170

... EOPIFR — End Of Packet Interrupt Flag Clear Writing a logic "1" to this bit clears the EOPIF flag. Writing a "0" has no effect. Reset clears this bit Writing 1 clears EOPIF effect Data Sheet 170 Universal Serial Bus Module (USB) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 171

... Software should set this bit when data is ready for data packet transmission. It must be cleared when no more data needs to be transmitted. If TX0E is "0" or TXD0F is "1", a NAK handshake will be returned for the next IN token. Reset clears this bit. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $002B Bit T0SEQ STALL0 ...

Page 172

... Setting this bit selects endpoint 2 to use the data registers. Data Sheet 172 $002F Bit T1SEQ ENDADD TX1E FRESUM TP1SIZ3 Figure 13-5. USB Control Register 1 (UCR1) Universal Serial Bus Module (USB Bit 0 TP1SIZ2 TP1SIZ1 TP1SIZ0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 173

... The TP1SIZ[3:0] is used to store the number of transmit data bytes from endpoint 1/2. The default size of transmit data is "0" after reset. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = The transmit buffer is used for endpoint The transmit buffer is used for endpoint Data is ready to be sent on endpoint 1 Data is not ready; respond with ACK 1 = Resume state forced on USB bus ...

Page 174

... SUSPND in the interrupt service routine Enable USB suspend mode 0 = Disable USB suspend mode Data Sheet 174 $002D Bit PULLEN SUSPND ENABLE2 ENABLE1 STALL2 TX1STR Figure 13-6. USB Control Register 2 (UCR2) Universal Serial Bus Module (USB Bit 0 STALL1 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 175

... USB Status Register (USR) Address: Read: Write: Reset: MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = Endpoint 2 enabled; and responds to IN tokens 0 = Endpoint 2 disabled 1 = Endpoint 1 enabled; and responds to IN tokens 0 = Endpoint 1 disabled 1 = Send STALL handshake on endpoint not send STALL handshake on endpoint Send STALL handshake on endpoint 1 ...

Page 176

... IN transaction occurred after SETUP or OUT RPSIZ[3:0] — Received Data Size The RPSIZ[3:0] indicates the number of received data bytes in a data packet. Reset will not affect these bits Data Sheet 176 Universal Serial Bus Module (USB) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 177

... These eight 8-bit buffers are loaded by user software with data to be sent on the USB bus on the next IN token directed at endpoint 1 or endpoint 2. The ENDADD bit in the USB control register 1 determines either endpoint 1 or endpoint 2 uses these buffers. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $0030–$0037 Bit Indeterminate after reset $0038– ...

Page 178

... Universal Serial Bus Module (USB) Data Sheet 178 Universal Serial Bus Module (USB) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 179

... It also provides the flexibility of hooking additional devices to an existing system for future expansion without adding extra hardware. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Registers .181 Multi-Master IIC Address Register (MMADR 182 Multi-Master IIC Control Register (MMCR) ...

Page 180

... Generic Pin Names: SDA SCL Data Sheet 180 Full MCU Pin Names: PTD6/IICSDA IICDATE bit in PDCR ($0049) PTD5/IICSCL IICSCLE bit in PDCR ($0049) Multi-Master IIC Interface (MMIIC) . The maximum DD Table 14-1. The generic Pin Selected for IIC Function By: MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 181

... Read: MMRD7 Multi-Master IIC Data Receive Register $004F Write: (MMDRR) Reset: 14.5 Registers Six registers are associated with the Multi-master IIC module, they are outlined in the following sections. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Bit MMALIF MMBB MMAST MMNAKIF MMAD7 MMAD6 ...

Page 182

... Reset clears this bit MMIIC calling address is $MMAD[7:4 MMIIC address is $MMAD[7:1] Data Sheet 182 $004B Bit MMAD7 MMAD6 MMAD5 MMAD4 MMIIC respond address is $00, and $MMAD[7:4]0 to $MMAD[7:4]F Multi-Master IIC Interface (MMIIC Bit 0 MMAD3 MMAD2 MMAD1 MMEXTAD MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 183

... This bit is set to disable the MMIIC from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. When MMTXAK is cleared, an acknowledge signal will be sent at the 9th clock bit. Reset clears this bit. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor $004C Bit MMEN ...

Page 184

... MMIIC is disabled. Reset clears this bit Start condition detected 0 = Stop condition detected or MMIIC is disabled Data Sheet 184 $004A Bit MMALIF MMBB MMAST MMNAKIF Multi-Master IIC Interface (MMIIC Bit 0 MMRW MMBR2 MMBR1 MMBR0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 185

... WAIT instruction places the MCU in WAIT mode, with CPU clock is halted. These bits are cleared upon reset. (See 14-3 . Baud Rate MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = Master mode operation 0 = Slave mode operation 1 = Master mode receive 0 = Master mode transmit Select.) ...

Page 186

... MMBR1 MMBR0 NOTE: CPU bus clock is external clock ÷ 6MHz $004D Bit MMTXIF MMATCH MMSRW MMRXAK Unimplemented Multi-Master IIC Interface (MMIIC) Baud Rate 750k 375k 187.5k 93.75k 46.875k 23.437k 11.719k 5.859k Bit 0 0 MMTXBE MMRXBF MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 187

... SDA line for the master to generate "stop" or "repeated start" condition. Reset sets this bit. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = Data transfer completed 0 = Data transfer in progress 1 = Received address matches MMADR 0 = Received address does not match 1 = Slave mode transmit ...

Page 188

... Data Sheet 188 $004E Bit MMTD7 MMTD6 MMTD5 MMTD4 Multi-Master IIC Interface (MMIIC Bit 0 MMTD3 MMTD2 MMTD1 MMTD0 MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 189

... In slave mode, the data in MMDRR is: MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor the module receives an acknowledge bit (MMRXAK = 0), after setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or the previous data in the output circuit has be transmitted and the receiving slave returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0) ...

Page 190

... MMBB flag. This is the only way to clear the MMBB flag by software if the module hangs up due STOP condition received. The MMIIC can resume operation again by setting the MMEN bit. Data Sheet 190 Figure 14-7. Multi-Master IIC Interface (MMIIC) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 191

... Slave Receive Mode START Address MMTXBE=0 MMRXBF=0 KEY: shaded data packets indicate a transmit by the MCU’s MMIIC module Figure 14-7. Data Transfer Sequences for Master/Slave Transmit/Receive Modes MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 0 ACK TX Data1 ACK MMTXBE=1 MMTXBE=1 MMTXIF=1 MMTXIF=1 Data2 → MMDTR Data3 → ...

Page 192

... Multi-Master IIC Interface (MMIIC) Data Sheet 192 Multi-Master IIC Interface (MMIIC) MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 193

... It also provides the flexibility of hooking additional devices to an existing system for future expansion without adding extra hardware. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Section 15. DDC12AB Interface Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 DDC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Registers .196 DDC Address Register (DADR) ...

Page 194

... Table 15-1. Pin Name Conventions DDC12AB Generic Pin Names: SDA SCL Data Sheet 194 Full MCU Pin Names: PTD2/DDCSDA DDCDATE bit in PDCR ($0049) PTD3/DDCSCL DDCSCLE bit in PDCR ($0049) DDC12AB Interface . The DD Table 15-1. Pin Selected for DDC Function By: MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 195

... Data Transmit Register Write: (DDTR) Reset: Read: DDC Data Receive Register $001B Write: (DDRR) Reset: Read: DDC2 Address Register $001C Write: (D2ADR) Reset: MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor Table 15-2. DDC I/O Register Summary Bit ALIF NAKIF DAD7 DAD6 DAD5 DEN DIEN ...

Page 196

... Reset sets a default value of $A0. Data Sheet 196 $0017 Bit DAD7 DAD6 DAD5 DAD4 Figure 15-1. DDC Address Register (DADR) DDC12AB Interface Bit 0 DAD3 DAD2 DAD1 EXTAD MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 197

... D2AD[7:1] should be set to the same value as DAD[7:1] in DADR if user application do not use DDC2BI. Reset clears all bits this register. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = DDC calling address is $DAD[7:4]0 DDC respond address is $00, and $DAD[7:4]0 to $DAD[7:4 DDC address id $DAD[7:1] $001C Bit 7 ...

Page 198

... DDC does not send acknowledge signals at 9th clock bit 0 = DDC sends acknowledge signal at 9th clock bit Data Sheet 198 $0018 Bit DEN DIEN Unimplemented Figure 15-3. DDC Control Register (DCR) request to CPU interrupt request to CPU DDC12AB Interface Bit 0 0 TXAK SCLIEN DDC1EN MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

Page 199

... CPU if the DIEN bit in DCR is also set. This bit is cleared by writing "0" reset. MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor 1 = SCLIF bit set will generate interrupt request to CPU 0 = SCLIF bit set will not generate interrupt request to CPU 1 = DDC1 protocol enabled 0 = DDC1 protocol disabled ...

Page 200

... When it is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode. Reset clears this bit Master mode receive 0 = Master mode transmit Data Sheet 200 DDC12AB Interface MC68HC908BD48 Rev. 2.1 — Freescale Semiconductor ...

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