MC68HC908GZ8MFJ Freescale Semiconductor, MC68HC908GZ8MFJ Datasheet
MC68HC908GZ8MFJ
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MC68HC908GZ16 MC68HC908GZ8 Data Sheet M68HC08 Microcontrollers MC68HC908GZ16 Rev. 4.0 10/2006 freescale.com ...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. ...
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... Corrected timer link connection from TIM2 channel 0 to TIM1 — Replaced note with unused pin termination text. and — Updated DC injection current Page Number(s) N/A N 181–212 N/A 289 291 302 N/A 303 311–314 205 209 210 110 26 121 133 155 289 291 Freescale Semiconductor ...
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... Chapter 17 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Chapter 18 Timebase Module (TBM 251 Chapter 19 Timer Interface Module (TIM 255 Chapter 20 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Chapter 21 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Chapter 22 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 303 Appendix A MC68HC908GZ8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 5 ...
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... List of Chapters MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Freescale Semiconductor ...
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... FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.4 FLASH Mass Erase Operation 2.6.5 FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.6 FLASH Block Protection 2.6.7 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Chapter 1 General Description and and DDA SSA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CGMXFC /V ...
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... Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Chapter 3 Analog-to-Digital Converter (ADC DDAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SSAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 REFL ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Chapter 4 Clock Generator Module (CGM) Freescale Semiconductor ...
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... Power-On Reset 6.3.5 Internal Reset 6.3.6 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.7 COPD (COP Disable 6.3.8 COPRS (COP Rate Select 6.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 SSA Chapter 5 Configuration Register (CONFIG) Chapter 6 9 ...
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... Keyboard Module During Break Interrupts 107 9.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.7.1 Keyboard Status and Control Register 107 9.7.2 Keyboard Interrupt Enable Register 108 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) Freescale Semiconductor ...
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... Timebase Module (TBM 113 10.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.14 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.14.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.14.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.15 Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.16 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Chapter 10 Low-Power Modes 11 ...
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... Transmit Buffer Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.13.1 MSCAN08 Module Control Register 142 12.13.2 MSCAN08 Module Control Register 143 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Chapter 11 Low-Voltage Inhibit (LVI) Chapter 12 MSCAN08 Controller (MSCAN08) Freescale Semiconductor ...
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... Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.2.3.4 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.2.3.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.2.4 System Integration Module (SIM) Reset Status Register 171 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Chapter 13 Input/Output (I/O) Ports Chapter 14 Resets and Interrupts 13 ...
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... Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.6 ESCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Chapter 15 Freescale Semiconductor ...
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... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 16.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16.5.1.3 Interrupt Status Registers 223 16.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Chapter 16 System Integration Module (SIM) 15 ...
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... I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.13.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.13.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 17.13.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.2 Features 251 18.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Chapter 17 Chapter 18 Timebase Module (TBM) Freescale Semiconductor ...
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... Break Module Registers 273 20.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 20.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 20.2.2.3 Break Status Register 275 20.2.2.4 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Chapter 19 Timer Interface Module (TIM) Chapter 20 Development Support 17 ...
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... Ordering Information and Mechanical Specifications 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 22.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 22.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 A.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 A.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 A.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Chapter 21 Electrical Specifications Chapter 22 Appendix A MC68HC908GZ8 Freescale Semiconductor ...
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... In-system programming (ISP security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 0. Device Memory Size 16 Kbytes user FLASH 8 Kbytes user FLASH ...
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... Up to 8-bit keyboard wakeup port depending on package choice • maximum current injection on all port pins to maintain input protection • Available packages: – 32-pin quad flat pack (LQFP) – 48-pin quad flat pack (LQFP) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Freescale Semiconductor ...
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... MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908GZ16. 1.4 Pin Assignments Figure 1-2 and Figure 1-3 illustrate the pin assignments for the 32-pin LQFP and 48-pin LQFP respectively. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor MCU Block Diagram 21 ...
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... PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1/CAN RX (1), (2) PTC0/CAN TX (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
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... PTE1/RxD PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK Figure 1-2. 32-Pin LQFP Pin Assignments RST 1 PTE0/TxD PTE1/RxD PTE2 PTE3 PTE4 PTE5 IRQ PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK 12 Figure 1-3. 48-Pin LQFP Pin Assignments MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor RST IRQ Pin Assignments ...
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... External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Chapter 8 External Interrupt (IRQ). MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev and MCU 0.1 μ Figure 1-4. Power Supply Bypassing Figure 1 Chapter 4 Freescale Semiconductor ...
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... PTD7–PTD4 can be individually programmed to be timer interface module (TIM1 and TIM2) pins. PTD7 is only available on the 48-pin LQFP package. See 19 Timer Interface Module (TIM), Input/Output (I/O) Ports. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor and V ) DDA SSA ) CGMXFC ...
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... Configuring unused pins as inputs and using external pull-up or pull-down resistors. Never connect unused pins directly to V Since some general-purpose I/O pins are not available on all packages, these pins must be terminated as well. Either method above are appropriate. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev and Freescale Semiconductor ...
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... BRKSCR • $FE0C; LVI status register, LVISR • $FF7E; FLASH block protect register, FLBPR Data registers are shown in Figure MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 2-2. Table 2 list of vector locations. Figure 2-1, includes: 27 ...
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... Figure 2-1. Memory Map RESERVED FLASH CONTROL REGISTER (FLCR) LVI STATUS REGISTER (LVISR) UNIMPLEMENTED 3 BYTES UNIMPLEMENTED 16 BYTES FOR A-FAMILY PART MONITOR ROM 350 BYTES UNIMPLEMENTED 85 BYTES FLASH VECTORS 44 BYTES Freescale Semiconductor ...
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... See page 209. Reset: Read: ESCI Arbiter Data $000B Register (SCIADAT) Write: See page 210. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 ...
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... SCTIE TCIE SCRIE ILIE SCTE TC SCRF IDLE Unimplemented R = Reserved Bit 0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF Unaffected Freescale Semiconductor ...
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... Register Low (T1CNTL) Write: See page 266. Reset: Read: Timer 1 Counter Modulo $0023 Register High (T1MODH) Write: See page 267. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Bit Unaffected by reset ...
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... Indeterminate after reset Bit Indeterminate after reset TOF 0 TOIE TSTOP 0 TRST Bit Bit Bit Bit Unimplemented R = Reserved Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit Unaffected Freescale Semiconductor ...
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... Reset: Read: PLL VCO Select Range $003A Register (PMRS) Write: See page 73. Reset: Read: $003B Reserved Write: Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Bit CH0F CH0IE MS0B MS0A Bit 15 14 ...
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... Programmer’s Model of Control Registers Reserved (40 bytes) MSC08 receive buffer Refer to 12.12 Programmer’s Model of Message Storage MSC08 transmitter buffer 0 Refer to 12.12 Programmer’s Model of Message Storage = Unimplemented R = Reserved Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD9 AD8 A3 AD2 AD1 AD0 0 MODE1 MODE0 Unaffected Freescale Semiconductor ...
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... Break Address Register High $FE09 (BRKH) Write: See page 274. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Bit MSC08 transmitter buffer 1 Refer to 12.12 Programmer’s Model of Message Storage MSC08 transmitter buffer 2 Refer to 12.12 Programmer’ ...
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... Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Bit Bit BRKE BRKA LVIOUT BPR7 BPR6 BPR5 BPR4 Unaffected by reset Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved Bit Bit BPR3 BPR2 BPR1 BPR0 U = Unaffected Freescale Semiconductor ...
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... Vector Priority Lowest Highest MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor . Table 2-1. Vector Addresses Vector Address $FFD4 MSCAN08 Transmit Vector (High) IF20 $FFD5 MSCAN08 Transmit Vector (Low) $FFD6 MSCAN08 Receive Vector (High) IF19 $FFD7 MSCAN08 Receive Vector (Low) $FFD8 ...
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... Program and erase operation operations are facilitated through control bits in FLASH control register (FLCR). Details for these operations appear later in this section. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev NOTE NOTE NOTE Freescale Semiconductor ...
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... FLASH block protect register • $FFD4–$FFFF; these locations are reserved for user-defined interrupt and reset vectors Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. A security feature prevents viewing of the FLASH contents. 2.6.2 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations ...
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... Any application can use this 4-ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1-ms page erase specification to get a shorter cycle time. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev NOTE Freescale Semiconductor ...
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... PROG 9. Repeat step 7 and 8 until all the bytes within the row are programmed. 1. When in monitor mode, with security sequence failed (see of any FLASH address. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor (1) within the FLASH memory address range. NOTE NOTE (Figure 2-4 NOTE 20 ...
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... This applies particularly to $FFD4–$FFDF. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev NOTE NOTE NOTE NOTE maximum or t maximum. t PROG 32) NVH PGS PROG Characteristics. NOTE CAUTION is defined as the HV ≤ t maximum HV Freescale Semiconductor ...
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... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...
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... BPR[7:0] — FLASH Block Protect Bits These eight bits represent bits [13: 16-bit memory address. Bit 15 and Bit 14 are 1s and bits [5:0] are 0s. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev NOTE NOTE BPR6 BPR5 BPR4 BPR3 the TST 2 1 Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...
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... FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode Standby mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 16-BIT MEMORY ADDRESS ...
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... Memory MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Freescale Semiconductor ...
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... I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC will return a logic 0. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 3-2. 47 ...
Page 48
... PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1/CAN RX (1), (2) PTC0/CAN TX (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 49
... The ADC input voltage must always be greater than DDAD Connect the V DDAD connect the V SSAD The V pin should be routed carefully for maximum noise immunity. DDAD MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor DDRBx PTBx DISABLE ADC DATA REGISTER ADC VOLTAGE IN (V ADIN ADC ADC CLOCK CLOCK GENERATOR ADIV2– ...
Page 50
... Finally, 8-bit truncation mode will place the eight MSBs in the ADC data register low, ADRL. The two LSBs are dropped. This mode of operation MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev ADC cycles ADC frequency Freescale Semiconductor ...
Page 51
... A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. 3.6 Low-Power Modes The WAIT and STOP instruction can put the MCU in low power-consumption standby modes. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor NOTE Figure 3-3. IDEAL 8-BIT CHARACTERISTIC WITH QUANTIZATION = ± ...
Page 52
... External filtering is often necessary to ensure a clean V DD NOTE carefully and place bypass REFH may improve common mode noise rejection. pin to the same voltage DDAD for good results. DDAD pin to the same voltage SSAD REFH REFH close and REFH Freescale Semiconductor for ...
Page 53
... When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit ADC interrupt enabled 0 = ADC interrupt disabled MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor ) REFL as its lower voltage reference pin. By default, connect the V REFL ...
Page 54
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Table 3-1. NOTE Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ↓ ↓ ↓ Table 3-1. Care should (1) Input Select PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6 PTB7/AD7 Unused V REFH V REFL ADC power off Freescale Semiconductor ...
Page 55
... All subsequent results will be lost until the ADRH and ADRL reads are completed. Address: $003D Bit 7 Read: 0 Write: Reset: Address: $003E Read: AD7 Write: Reset: Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset = Unimplemented ...
Page 56
... Figure 3-8. ADC Data Register High (ADRH) and Low (ADRL) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset = Unimplemented Unaffected by reset AD8 AD7 AD6 AD5 Unaffected by reset = Unimplemented 2 1 Bit 0 AD4 AD3 AD2 ADRH 2 1 Bit ADRL AD4 AD3 AD2 Freescale Semiconductor ...
Page 57
... MODE1 and MODE0 select among four modes of operation. The manner in which the ADC conversion results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns right-justified mode 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified signed data mode MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor ADIV1 ADIV0 ADICLK ...
Page 58
... Analog-to-Digital Converter (ADC) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Freescale Semiconductor ...
Page 59
... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 4-1 shows the structure of the CGM. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 59 ...
Page 60
... VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG AUTOMATIC INTERRUPT MODE CONTROL CONTROL AUTO ACQ PLLIE PLLF Figure 4-1. CGM Block Diagram CGMXCLK (TO: SIM, TIMTB15A, ADC) A CGMOUT CLOCK ÷ 2 SELECT (TO SIM CIRCUIT SIMDIV2 * WHEN CGMOUT = B (FROM SIM) CGMVCLK CGMINT (TO SIM) Freescale Semiconductor ...
Page 61
... The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the reference clock, CGMRCLK. Therefore, the speed of the lock detector is directly proportional to the reference MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor VRS , (71.4 kHz) times a linear factor, L, and a power-of-two factor PLL ...
Page 62
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev 4.5.2 PLL Bandwidth Control 4.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of Modes.) 4.8 Acquisition/Lock Time Specifications 4.8 Acquisition/Lock Time Specifications Register.) Register.) 4.5.2 PLL 4.3.8 Base Clock Selector for for Freescale Semiconductor ...
Page 63
... The relationship between the VCO frequency, f reference frequency, f RCLK N, the range multiplier, must be an integer. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor , after entering tracking mode before selecting the PLL as the AL Table 4-1. Variable Definitions Definition ...
Page 64
... VCLK L = Round NOM VRS NOM E × NOM ≤ -------------------------- - f – f VRS VCLK VCLK VRS VCLKDES NOTE to a value determined RCLK Chapter 21 Electrical and f . VCLK BUS Table 4- (1) 2 VRS and f . For proper operation, VCLKDES , and f must be as close as possible VRS Freescale Semiconductor . The ...
Page 65
... L is programmed This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Table 4-3. Numeric Example f RCLK ...
Page 66
... Note: Filter network in box can be replaced with a single capacitor, but will degrade stability. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev CGMXCLK CGMXFC OSC2 Component Filter C 2 Figure 4-2. CGM External Connections Figure V V SSA DDA V DD CBYP C F2 0.1 μF Freescale Semiconductor 4-2. ...
Page 67
... If this bit is set, the Oscillator continues running during stop mode. If this bit is not set (default), the oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 4-2.) NOTE ...
Page 68
... PLL VCO range select register (PMRS) (See 4.5.5 PLL VCO Range Select Figure 4 summary of the CGM registers. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Figure 4-2 shows only the logical relation of CGMXCLK to OSC1 Register.) High.) Low.) Register.) ) and comes XCLK Freescale Semiconductor ...
Page 69
... The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: PLLIE Write: Reset Unimplemented MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Bit PLLF PLLIE PLLON LOCK AUTO ...
Page 70
... BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See 4.3.8 Base Clock Selector MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev NOTE NOTE Circuit.). 4.3.8 Base Clock Selector 4.3.8 Base Clock Freescale Semiconductor ...
Page 71
... This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit Automatic bandwidth control 0 = Manual bandwidth control MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor VRS 4.3.3 PLL Circuits, Register.) ...
Page 72
... PLL is on (PLLON = 1). PMSH[7:4] — Unimplemented Bits These bits have no function and always read as logic 0s. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev MUL11 4.3.3 PLL Circuits and 4.3.6 Programming the NOTE 2 1 Bit 0 MUL10 MUL9 MUL8 PLL.) A value of $0000 in Freescale Semiconductor ...
Page 73
... The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: $003A Bit 7 Read: VRS7 Write: Reset: 0 Figure 4-8. PLL VCO Range Select Register (PMRS) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor MUL6 MUL5 MUL4 MUL3 ...
Page 74
... PLL, and 4.5.1 PLL Control . VRS7–VRS0 cannot be written when the PLLON bit in the VRS Exceptions.) A value of $00 in the VCO range select Exceptions.). Reset initializes the register to $40 NOTE NOTE 4.3.6 Register.), controls the 4.3.8 Base Freescale Semiconductor ...
Page 75
... If the system is operating at 1 MHz and suffers a –100-kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the 100-kHz step input. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 16.7.3 Break Flag Control Register. Special Modes ...
Page 76
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev PLL.) 4.8.3 Choosing a . The power supply potential alters the DDA Time, the external filter network is critical to the Figure 4-9 Figure 4-9 (A). Refer to Table 4-5 . RCLK . (See XCLK Filter.) (B) can be replaced by a for recommended filter Freescale Semiconductor ...
Page 77
... CGMXFC SSA (A) Table 4-5. Example Filter Component Values f RCLK 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor CGMXFC Figure 4-9. PLL Filter 8.2 nF 820 pF 4.7 nF 470 pF 3.3 nF 330 pF 2.2 nF 220 pF 1.8 nF 180 pF 1.5 nF 150 pF 1 ...
Page 78
... Clock Generator Module (CGM) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Freescale Semiconductor ...
Page 79
... Address: $001E Bit 7 6 Read Write: Reset Note: MSCANEN is only reset via POR (power-on reset). = Unimplemented Figure 5-1. Configuration Register 2 (CONFIG2) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor – – 2 COPCLK cycles) NOTE Figure 5-1 and MSCANEN TMCLKSEL OSCENINSTOP ESCIBDSRC ...
Page 80
... Chapter 4 Clock Generator Module (CGM) (CGM). This function is used to keep the timebase running while Chapter 18 Timebase Module Module – 2 COPCLK cycles 18 4 – 2 COPCLK cycles 2 1 Bit 0 SSREC STOP COPD (TBM). When clear, oscillator will cease Chapter 15 Enhanced Serial Chapter 6 Computer Operating Freescale Semiconductor for ...
Page 81
... LVI is not protecting the MCU. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction STOP instruction enabled 0 = STOP instruction treated as illegal opcode MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Chapter 11 Low-Voltage Inhibit Chapter 11 Low-Voltage Inhibit Chapter 11 Low-Voltage Inhibit NOTE NOTE Functional Description (LVI) ...
Page 82
... Configuration Register (CONFIG) COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev Chapter 6 Computer Operating Properly (COP) Module. Freescale Semiconductor ...
Page 83
... COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 16 System Integration Module (SIM) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details ...
Page 84
... The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. 6.3.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev NOTE . During the break state, TST NOTE Figure 6- – – 2 6.4 COP Freescale Semiconductor ...
Page 85
... The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes. 6.7.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Low byte of reset vector ...
Page 86
... STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when V MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev present on the RST pin. TST Freescale Semiconductor ...
Page 87
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 87 ...
Page 88
... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...
Page 89
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor ...
Page 90
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev NOTE 2 1 Bit Freescale Semiconductor ...
Page 91
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 91 ...
Page 92
... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 – – IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 – – IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
Page 93
... CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← (PC rel ? IRQ = 0 – ...
Page 94
... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 – – – IX1 SP1 9E6C ff 5 Freescale Semiconductor ...
Page 95
... ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...
Page 96
... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...
Page 97
... Memory location N Negative bit 7.8 Opcode Map See Table 7-2. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← (SP) – 1; Push (CCR) SP ← ...
Page 98
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 99
... The external interrupt pin is falling-edge triggered and is software-configurable to be either falling-edge or falling-edge and low-level triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, software clear, or reset occurs. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 99 ...
Page 100
... V DD CLR IMASK MODE Figure 8-1. IRQ Module Block Diagram NOTE Bit Unimplemented Figure 8-2. IRQ I/O Register Summary TO CPU FOR BIL/BIH INSTRUCTIONS IRQF IRQ SYNCHRONIZER INTERRUPT REQUEST TO MODE HIGH SELECT VOLTAGE LOGIC DETECT IRQF 0 IMASK ACK Freescale Semiconductor Bit 0 MODE 0 ...
Page 101
... To protect CPU interrupt flags during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor NOTE Support. IRQ Pin ...
Page 102
... This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 102 IRQF Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...
Page 103
... If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 103 ...
Page 104
... PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1/CAN RX (1), (2) PTC0/CAN TX (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 105
... Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor ACKK V DD CLR ...
Page 106
... Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 106 NOTE Freescale Semiconductor ...
Page 107
... These read-only bits always read as logic 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit Keyboard interrupt pending keyboard interrupt pending MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 9.7.1 Keyboard Status and Control ...
Page 108
... Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 108 KBIE6 KBIE5 KBIE4 KBIE3 Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
Page 109
... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Chapter 5 Chapter 5 Configuration 109 ...
Page 110
... CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop is shut off, but the oscillator will continue to operate in stop mode. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 110 Freescale Semiconductor ...
Page 111
... The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Computer Operating Properly Module (COP) 111 ...
Page 112
... The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 112 Freescale Semiconductor ...
Page 113
... The MSCAN08 module is inactive in stop mode. The STOP instruction does not affect MSCAN08 register states. Because the internal clock is inactive during stop mode, entering stop mode during an MSCAN08 transmission or reception results in invalid data. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Timer Interface Module (TIM1 and TIM2) 113 ...
Page 114
... MSCAN module interrupt — A CPU interrupt request from the MSCAN08 loads the program counter with the contents of: – $FFD4 and $FFD5; MSCAN08 transmitter – $FFD6 and $FFD7; MSCAN08 receiver – $FFD8 and $FFD9; MSCAN08 error – $FFDA and $FFDB; MSCAN08 wakeup MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 114 voltage resets TRIPF Freescale Semiconductor ...
Page 115
... Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor TRIPF NOTE Exiting Stop Mode voltage resets the ...
Page 116
... Low-Power Modes MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 116 Freescale Semiconductor ...
Page 117
... TRIPR V which will re-trigger the power-on reset and reset the trip point to 3-V operation. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI ...
Page 118
... V DD TRIPF to remain above the V level, enabling LVI resets allows the LVI TRIPF falls below the V level. In the configuration register, the DD TRIPF , which causes the MCU TRIPR LVISTOP FROM CONFIG1 LVI RESET level, software can monitor V DD Freescale Semiconductor Bit polling ...
Page 119
... Reset clears the LVIOUT bit. V 11.5 LVI Interrupts The LVI module does not generate interrupt requests. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor fall below V ), the LVI will maintain a reset condition until DD TRIPF . This prevents a condition in which the MCU is ...
Page 120
... MCU out of wait mode. 11.6.2 Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 120 Freescale Semiconductor ...
Page 121
... Programmable MSCAN08 clock source either CPU bus clock or crystal oscillator output • Programmable link to timer interface module 1, channel 0, for time-stamping and network synchronization • Low-power sleep mode MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 121 ...
Page 122
... PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1/CAN RX (1), (2) PTC0/CAN TX (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE ). The CAN output TX TX Freescale Semiconductor ...
Page 123
... Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor CAN STATION 1 CAN NODE 2 MCU ...
Page 124
... The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 124 12.4.2 Receive Structures. 12.12 Programmer’s Model of Message 1), where the MSCAN08 treats its own messages exactly like Figure 12-3). While the Storage. 12.5 Identifier (2) . The user’s receive handler Freescale Semiconductor ...
Page 125
... Figure 12-3. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Programmer’s Model of Message an 8-bit “local priority” field (PRIO) (see MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor RxBG RxFG RXF TXE Tx0 PRIO ...
Page 126
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 126 (CRFLG)) and two bits in the identifier acceptance control register (see Register). These identifier hit flags (IDHIT1 and IDHIT0) Figure 12-4 12.13.7 (1) when TXE is set and 12.13.5 shows how the 32-bit filter bank Freescale Semiconductor ...
Page 127
... AM7 CIDMR0 AC7 CIDAR0 ID ACCEPTED (FILTER 0 HIT) AM7 CIDMR2 AC7 CIDAR2 ID ACCEPTED (FILTER 1 HIT) Figure 12-5. Dual 16-Bit Maskable Acceptance Filters MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor ID20 IDR1 ID15 ID14 IDR2 ID3 ID2 IDR1 IDE ID10 IDR2 AM7 ...
Page 128
... AM0 AC7 CIDAR3 AC0 ID ACCEPTED (FILTER 3 HIT) Figure 12-6. Quadruple 8-Bit Maskable Acceptance Filters MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 128 ID20 IDR1 ID15 ID14 IDR2 ID2 IDR1 IDE ID10 IDR2 ID7 ID6 IDR3 RTR ID3 ID10 IDR3 ID3 Freescale Semiconductor ...
Page 129
... Interrupt Vectors The MSCAN08 supports four interrupt vectors as shown in relative interrupt priority are dependent on the chip integration and to be defined. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 12.13.5 MSCAN08 Receiver Flag Register (CRFLG) Register. 12.4.2 Receive Structures, has occurred. ...
Page 130
... Local Source Mask WUPIF WUPIE RWRNIF RWRNIE TWRNIF TWRNIE RERRIF RERRIE TERRIF TERRIE BOFFIF BOFFIE OVRIF OVRIE RXF RXFIE TXE0 TXEIE0 TXE1 TXEIE1 TXE2 TXEIE2 0) serves as a lock to protect the following registers: Global Mask I bit 12.13.1 Table 12-2 Freescale Semiconductor ...
Page 131
... The MCU clears the SLPRQ bit, or • The MCU sets the SFTRES bit The MCU cannot clear the SLPRQ bit before the MSCAN08 is in sleep mode (SLPAK=1). MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor . CPU Mode STOP (1) SLPAK = X SFTRES = X Figure 12-7) ...
Page 132
... The recommended procedure is to bring the MSCAN08 into sleep mode before the STOP instruction is executed. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 132 MSCAN08 RUNNING SLPRQ = 0 SLPAK = 0 MCU SLEEP REQUEST SLPRQ = 1 SLPAK = 0 MSCAN08 NOTE NOTE 12.13.1 MSCAN08 Module Freescale Semiconductor ...
Page 133
... The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 12.13.2 MSCAN08 Module Control Register 0) defines whether the MSCAN08 is connected to the output of the ...
Page 134
... For further explanation of the underlying concepts please refer to ISO/DIS 11 519-1, Section 10.3. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 134 CGMXCLK ÷ 2 ÷ 2 PLL CLKSRC Figure 12-8. Clocking Scheme NOTE f MSCANCLK Presc value (1) (see Figure 12-9 Bit rate = No. of time quanta CGMOUT (TO SIM) BCS (2 * BUS FREQUENCY) MSCANCLK PRESCALER (1 ... 64) Freescale Semiconductor ...
Page 135
... Segment MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor and 12.13.4 MSCAN08 Bus Timing Register NOTE NRZ SIGNAL TIME SEGMENT 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8... 25 TIME QUANTA = 1 BIT TIME SAMPLE POINT (SINGLE OR TRIPLE SAMPLING) Table 12-3. Time Segment Syntax Time TSEG2 Segment 2 ...
Page 136
... RESERVED 5 BYTES $050D $050E ERROR COUNTERS 2 BYTES $050F $0510 IDENTIFIER FILTER 8 BYTES $0517 $0518 RESERVED 40 BYTES $053F $0540 RECEIVE BUFFER $054F $0550 TRANSMIT BUFFER 0 $055F $0560 TRANSMIT BUFFER 1 $056F $0570 TRANSMIT BUFFER 2 $057F Figure 12-10. MSCAN08 Memory Map Freescale Semiconductor ...
Page 137
... The foreground receive buffer can be read anytime but cannot be written. The transmit buffers can be read or written anytime. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Programmer’s Model of Message Storage Register Name IDENTIFIER REGISTER 0 ...
Page 138
... ID1 ID0 RTR DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 Freescale Semiconductor ...
Page 139
... In case of a transmit buffer, this flag defines the setting of the RTR bit to be sent Remote frame 0 = Data frame MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Bit ID10 ...
Page 140
... In case more than one buffer has the same lowest priority, the message buffer with the lower index number wins. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 140 Table 12-5. Data Length Codes Data Length Code DLC2 DLC1 DLC0 PRIO6 PRIO5 PRIO4 PRIO3 Unaffected by reset Table 12-5 Data Byte Count Bit 0 PRIO2 PRIO1 PRIO0 Freescale Semiconductor ...
Page 141
... Read: $050E CRXERR RXERR7 Write: Read: $050F CTXERR TXERR7 Write: Read: $0510 CIDAR0 Write: Read: $0511 CIDAR1 Write: Figure 12-15. MSCAN08 Control Register Structure MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor SYNCH SJW0 BRP5 BRP4 TSEG22 TSEG21 TSEG20 RWRNIF TWRNIF ...
Page 142
... AM4 = Unimplemented SYNCH TLNKEN Unimplemented Bit 0 AC3 AC2 AC1 AC0 AC3 AC2 AC1 AC0 AM3 AM2 AM1 AM0 AM3 AM2 AM1 AM0 AM3 AM2 AM1 AM0 AM3 AM2 AM1 AM0 R = Reserved 2 1 Bit 0 SLPAK SLPRQ SFTRES 12.9 Timer Freescale Semiconductor Link). ...
Page 143
... In this state the MSCAN08 ignores the bit sent during the ACK slot of the CAN frame Acknowledge field to insure proper reception of its own message. Both transmit and receive interrupts are generated Activate loop back self-test mode 0 = Normal operation MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 12.8.1 MSCAN08 Sleep ...
Page 144
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 144 Function). Figure Figure NOTE SJW0 BRP5 BRP4 BRP3 SJW0 clock, which is used to build up the individual bit timing, q 12.10 Clock 12-8). 12-8 Bit 0 BRP2 BRP1 BRP0 clock cycles q Synchronization Jump Width 1 T cycle cycle cycle cycle q Freescale Semiconductor System). ...
Page 145
... Bit time = The CBTR1 register can only be written if the SFTRES bit in the MSCAN08 module control register is set this case PHASE_SEG1 must be at least 2 time quanta. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Table 12-7. Baud Rate Prescaler BRP3 BRP2 BRP1 ...
Page 146
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 146 Table 12-8. Time Segment Values Time TSEG22 Segment 1 ( Cycle q ( Cycles q ( Cycles Cycles Cycles 1 q Table 12-4 for valid settings RWRNIF TWRNIF RERRIF TERRIF Time TSEG21 TSEG20 Segment Bit 0 BOFFIF OVRIF RXF ( not Freescale Semiconductor (1) Cycle Cycles . . Cycles ...
Page 147
... Condition to set the flag: RERRIF = (127 → REC → 255) & BOFFIF 3. Condition to set the flag: TERRIF = (128 → TEC → 255) & BOFFIF MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Programmer’s Model of Control Registers ( not masked, an error interrupt is pending (3) ...
Page 148
... A receive buffer full (successful message reception) event will result in a receive interrupt interrupt will be generated from this event. The CRIER register is held in the reset state when the SFTRES bit in CMCR0 is set. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 148 RWRNIE TWRNIE RERRIE TERRIE NOTE 2 1 Bit 0 BOFFIE OVRIE RXFIE Freescale Semiconductor ...
Page 149
... The associated message buffer is full (loaded with a message due for transmission). To ensure data integrity, no registers of the transmit buffers should be written to while the associated TXE flag is cleared. The CTFLG register is held in the reset state when the SFTRES bit in CMCR0 is set. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor ABTAK2 ...
Page 150
... Write: Reset: 0 Figure 12-24. Identifier Acceptance Control Register (CIDAC) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 150 ABTRQ2 ABTRQ1 ABTRQ0 Unimplemented NOTE NOTE IDAM1 IDAM0 Unimplemented 2 1 Bit 0 TXEIE2 TXEIE1 TXEIE0 12.13.7 MSCAN08 Transmitter Flag 2 1 Bit 0 0 IDHIT1 IDHIT0 Freescale Semiconductor ...
Page 151
... Reset: 0 Figure 12-25. Receiver Error Counter (CRXERR) This read-only register reflects the status of the MSCAN08 receive error counter. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor summarizes the different settings. In “filter closed” mode no messages IDAM0 Identifier Acceptance Mode 0 Single 32-bit acceptance filter ...
Page 152
... Unaffected by reset AC6 AC5 AC4 AC3 Unaffected by reset AC6 AC5 AC4 AC3 Unaffected by reset (CIDAR0–CIDAR3 Bit 0 TXERR2 TXERR1 TXERR0 Bit 0 AC2 AC1 AC0 2 1 Bit 0 AC2 AC1 AC0 2 1 Bit 0 AC2 AC1 AC0 2 1 Bit 0 AC2 AC1 AC0 Freescale Semiconductor ...
Page 153
... Ignore corresponding acceptance code register bit Match corresponding acceptance code register and identifier bits. The CIDMR0–CIDMR3 registers can be written only if the SFTRES bit in the CMCR0 is set MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor NOTE ...
Page 154
... MSCAN08 Controller (MSCAN08) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 154 Freescale Semiconductor ...
Page 155
... See page 160. Reset: Read: Port C Data Register $0002 (PTC) Write: See page 162. Reset: Read: Port D Data Register $0003 (PTD) Write: See page 164. Reset: MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTB7 PTB6 PTB5 1 PTC6 PTC5 ...
Page 156
... PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 Unimplemented Bit 0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Freescale Semiconductor ...
Page 157
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor DDR Module Control DDRA0 KBIE0 DDRA1 KBIE1 DDRA2 KBIE2 DDRA3 KBIE3 KBD DDRA4 KBIE4 DDRA5 KBIE5 DDRA6 KBIE6 DDRA7 KBIE7 DDRB0 DDRB1 DDRB2 DDRB3 ADC ADCH4–ADCH0 DDRB4 DDRB5 DDRB6 DDRB7 DDRC0 MSCAN08 ...
Page 158
... PTA6 PTA5 PTA4 PTA3 Unaffected by reset KBD6 KBD5 KBD4 KBD3 Figure 13-2. Port A Data Register (PTA) Chapter 9 Keyboard Interrupt Module (KBI DDRA6 DDRA5 DDRA4 DDRA3 NOTE 2 1 Bit 0 PTA2 PTA1 PTA0 KBD2 KBD1 KBD0 2 1 Bit 0 DDRA2 DDRA1 DDRA0 Freescale Semiconductor ...
Page 159
... DDRA is configured for output mode. Address: $000D Bit 7 Read: PTAPUE7 Write: Reset: 0 Figure 13-5. Port A Input Pullup Enable Register (PTAPUE) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor DDRAx RESET PTAx V DD INTERNAL PULLUP DEVICE Figure 13-4. Port A I/O Circuit Table 13-2 summarizes the operation of the port A pins ...
Page 160
... DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 160 PTB6 PTB5 PTB4 PTB3 Unaffected by reset AD6 AD5 AD4 AD3 Figure 13-6. Port B Data Register (PTB) for more information. NOTE 2 1 Bit 0 PTB2 PTB1 PTB0 AD2 AD1 AD0 Freescale Semiconductor ...
Page 161
... DDRB PTB I/O Pin Bit Bit Mode ( Input, Hi Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor DDRB6 DDRB5 DDRB4 DDRB3 NOTE DDRBx RESET PTBx Figure 13-8. Port B I/O Circuit Table 13-3 summarizes the operation of the port B pins ...
Page 162
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 162 NOTE PTC6 PTC5 PTC4 PTC3 Unaffected by reset Figure 13-9. Port C Data Register (PTC) Chapter 12 MSCAN08 Controller (MSCAN08 DDRC6 DDRC5 DDRC4 DDRC3 Bit 0 PTC2 PTC1 PTC0 CAN CAN RX TX –PTC0/CAN pins are MSCAN08 Bit 0 DDRC2 DDRC1 DDRC0 Freescale Semiconductor ...
Page 163
... Don’t care 2. I/O pin pulled internal pullup device Writing affects data register, but does not affect input. 4. Hi-Z = High impedance MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor NOTE DDRCx RESET PTCx V DD INTERNAL PULLUP DEVICE Figure 13-11. Port C I/O Circuit Table 13-4 summarizes the operation of the port C pins ...
Page 164
... I/O pins or general-purpose I/O pins. See MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 164 PTCPUE5 PTCPUE4 PTCPUE3 PTD6 PTD5 PTD4 PTD3 Unaffected by reset T2CH0 T1CH1 T1CH0 SPSCK Chapter 19 Timer Interface Module 2 1 Bit 0 PTCPUE2 PTCPUE1 PTCPUE0 Bit 0 PTD2 PTD1 PTD0 MOSI MISO SS (TIM). Freescale Semiconductor ...
Page 165
... Corresponding port D pin configured as input Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from Figure 13-15 shows the port D I/O logic. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Chapter 19 Timer Interface Module Table 13- ...
Page 166
... Accesses to DDRD I/O Pin Mode Read/Write (2) DDRD7–DDRD0 Input (4) DDRD7–DDRD0 Input, Hi-Z Output DDRD7–DDRD0 PTDPUE5 PTDPUE4 PTDPUE3 PTDx Accesses to PTD Read Write Pin PTD7–PTD0 Pin PTD7–PTD0 PTD7–PTD0 PTD7–PTD0 2 1 Bit 0 PTDPUE2 PTDPUE1 PTDPUE0 Freescale Semiconductor (3) (3) ...
Page 167
... Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a logic DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor ...
Page 168
... Figure 13-19. Port E I/O Circuit Table 13-6 summarizes the operation of the port E pins. Table 13-6. Port E Pin Functions Accesses to DDRE Read/Write (2) DDRE5–DDRE0 DDRE5–DDRE0 2 1 Bit 0 DDRE2 DDRE1 DDRE0 PTEx Accesses to PTE Read Write (3) Pin PTE5–PTE0 PTE5–PTE0 PTE5–PTE0 Freescale Semiconductor ...
Page 169
... All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor , generates an external reset. An external reset sets the RL ...
Page 170
... Sets the LVI bit in the SIM reset status register MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 170 4096 32 CYCLES CYCLES Figure 14-1. Power-On Reset Recovery is below the LVI DD pin the DD DD voltage TRIPR voltage and during the oscillator TRIPR Freescale Semiconductor ...
Page 171
... POR or read of SRSR since any reset ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR since any reset MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor at that time, then the PIN bit in the SRSR may be set IH NOTE 6 ...
Page 172
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 172 • • • CONDITION CODE REGISTER 1 ACCUMULATOR 2 (1) INDEX REGISTER (LOW BYTE) 3 PROGRAM COUNTER (HIGH BYTE) 4 PROGRAM COUNTER (LOW BYTE) 5 • • • $00FF DEFAULT ADDRESS ON RESET Figure 14-3. Interrupt Stacking Order UNSTACKING ORDER Freescale Semiconductor ...
Page 173
... A software interrupt pushes PC onto the stack. An SWI does not push PC – hardware interrupt does. 14.3.2.2 Break Interrupt The break module causes the CPU to execute an SWI instruction at a software-programmable break point. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE ...
Page 174
... INSTRUCTION MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 174 YES BREAK ? NO NO YES IRQ ? NO YES CGM ? NO OTHER YES ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR SWI YES ? NO RTI YES UNSTACK CPU REGISTERS ? NO EXECUTE INSTRUCTION Figure 14-5. Interrupt Processing SET I BIT Freescale Semiconductor ...
Page 175
... MSCAN08 error MSCAN08 receiver MSCAN08 transmitter 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction highest priority MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Table 14-1. Interrupt Sources INT Register (1) Flag Mask ...
Page 176
... SS pin goes low at any time with the MODFEN bit set. The error interrupt enable bit, ERRIE, enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and control register. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 176 Freescale Semiconductor ...
Page 177
... Analog-to-Digital Converter (ADC) When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Interrupts 177 ...
Page 178
... MSCAN08 has gone to error passive state. The transmit error passive interrupt enable bit, TERRIE, enables TERRIF to generate MSCAN08 error CPU interrupt requests. TERRIF is in MSCAN08 receiver flag register. TERRIE is in MSCAN08 receiver interrupt enable register. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 178 Freescale Semiconductor ...
Page 179
... SCI receive SCI transmit Keyboard ADC conversion complete Timebase MSCAN08 wakeup MSCAN08 error MSCAN08 receive MSCAN08 transmit MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Table 14-2. Interrupt Source Flags Interrupt Interrupt Status Source Register Flag Interrupts Table 14-2 summarizes the — ...
Page 180
... Bits 7–6 — Always read 0 MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 180 IF5 IF4 IF3 IF2 Reserved IF13 IF12 IF11 IF10 Reserved IF20 IF19 IF18 Reserved 2 1 Bit 0 IF1 Table 14- Bit 0 IF9 IF8 IF7 Table 14- Bit 0 IF17 IF16 IF15 Table 14-2. Freescale Semiconductor ...
Page 181
... Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 181 ...
Page 182
... PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1/CAN RX (1), (2) PTC0/CAN TX (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 183
... The baud rate clock source for the ESCI can be selected via the configuration bit, ESCIBDSRC, of the CONFIG2 register ($001E). For reference, a summary of the ESCI module input/output registers is provided in MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Table 15-1 shows the full names and the generic names of the Table 15-1. Pin Name Conventions ...
Page 184
... BKF ENSCI RPF PRE- BAUD RATE SCALER GENERATOR DATA SELECTION ÷ 16 CONTROL ESCI DATA RxD REGISTER SCI_TxD TRANSMIT SHIFT REGISTER BUS_CLK TXINV ACLK BIT IN SCIACTL ORIE NEIE FEIE PEIE LOOPS ENSCI TRANSMIT CONTROL M LINT WAKE ILTY PEN PTY Freescale Semiconductor TxD ...
Page 185
... ESCI Data Register $0018 (SCDR) Write: See page 204. Reset: Read: ESCI Baud Rate Register $0019 (SCBR) Write: See page 204. Reset: Figure 15-3. ESCI I/O Register Summary MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Bit PDS2 PDS1 PDS0 PSSB4 ALOST AM1 ...
Page 186
... PARITY GENERATION T8 SCTE SCTE SCTIE SCTIE TC TC TCIE TCIE Figure 15-5. ESCI Transmitter Figure 15-4. NEXT START BIT STOP BIT PARITY OR DATA NEXT BIT START BIT BIT 8 STOP BIT Figure SCI_TxD TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI TE LINT Freescale Semiconductor 15-3. ...
Page 187
... When LINR is set in SCBR, the ESCI recognizes a break character when a start bit is followed logic 0 data bits and a logic 0 where the stop bit should be, resulting in a total consecutive logic 0 data bits. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Functional Description 187 ...
Page 188
... Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 188 NOTE NOTE 1. Freescale Semiconductor ...
Page 189
... RPF PDS1 PDS0 M PSSB4 WAKE PSSB3 ILTY PSSB2 PSSB1 PEN PSSB0 PTY Figure 15-6. ESCI Receiver Block Diagram MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor INTERNAL BUS SCR1 SCR2 SCR0 BAUD ÷ 16 DIVIDER DATA H RECOVERY ALL ZEROS WAKEUP LOGIC PARITY ...
Page 190
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 190 START BIT START BIT START BIT DATA QUALIFICATION VERIFICATION SAMPLING Figure 15-7. Receiver Data Sampling Table 15-2. Start Bit Verification Start Bit Verification 000 Yes 001 Yes 010 Yes LSB Noise Flag Freescale Semiconductor ...
Page 191
... To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. summarizes the results of the stop bit samples. RT8, RT9, and RT10 Samples MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Start Bit Verification 011 No 100 ...
Page 192
... MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 192 MSB STOP DATA SAMPLES Figure 15-8. Slow Data Figure 15-8, the receiver counts 154 RT cycles at the point when 154 147 – × 100 = 4.54% ------------------------- - 154 Figure 15-8, the receiver counts 170 RT cycles at the point when Freescale Semiconductor ...
Page 193
... So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor 170 163 – × ...
Page 194
... Parity error (PE) — The PE bit in SCS1 is set when the ESCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate ESCI error CPU interrupt requests. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 194 NOTE Freescale Semiconductor ...
Page 195
... The PTE1/RxD pin is the serial data input to the ESCI receiver. The ESCI shares the PTE1/RxD pin with port E. When the ESCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor Support. Low-Power Modes 195 ...
Page 196
... This read/write bit enables the ESCI and the ESCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in ESCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit ESCI enabled 0 = ESCI disabled MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 196 ENSCI TXINV M WAKE Bit 0 ILTY PEN PTY Freescale Semiconductor ...
Page 197
... MSB position (see Table 15-3). Reset clears the PEN bit Parity function enabled 0 = Parity function disabled MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor NOTE Table 15-5. Character Format Selection Character Format Start Bits Data Bits Parity ...
Page 198
... SCRIE bit in SCC2 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE bit SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 198 NOTE TCIE SCRIE ILIE Bit 0 RE RWU SBK Freescale Semiconductor ...
Page 199
... No break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the ESCI to send a break character instead of a preamble. MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 Freescale Semiconductor NOTE NOTE NOTE I/O Registers ...
Page 200
... This read/write bit enables ESCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE ESCI error CPU interrupt requests from PE bit enabled 0 = ESCI error CPU interrupt requests from PE bit disabled MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 200 ORIE Unimplemented R = Reserved 2 1 Bit 0 NEIE FEIE PEIE Unaffected Freescale Semiconductor ...