C8051F020 Silicon Laboratories Inc, C8051F020 Datasheet
C8051F020
Specifications of C8051F020
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C8051F020 Summary of contents
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... Bytes FLASH; In-System programmable in 512-byte Sectors - External 64k Byte Data Memory Interface (programma- ble multiplexed or non-multiplexed modes) DIGITAL PERIPHERALS - 8 Byte-Wide Port I/O (C8051F020/2); 5V tolerant - 4 Byte-Wide Port I/O (C8051F021/3); 5V tolerant - Hardware SMBus™ (I Two UART Serial Ports Available Concurrently - Programmable 16-bit Counter/Timer Array with ...
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... C8051F020/1/2/3 2 Notes Rev. 1.4 ...
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... Analog to Digital Converter...................................................................................29 1.9. Comparators and DACs...................................................................................................30 2. ABSOLUTE MAXIMUM RATINGS ..................................................................................31 3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................32 4. PINOUT AND PACKAGE DEFINITIONS........................................................................33 5. ADC0 (12-BIT ADC, C8051F020/1 ONLY) ........................................................................43 5.1. Analog Multiplexer and PGA..........................................................................................43 5.2. ADC Modes of Operation ...............................................................................................44 5.2.1. Starting a Conversion.............................................................................................44 5.2.2. Tracking Modes .....................................................................................................45 5 ...
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... C8051F020/1/2/3 10. VOLTAGE REFERENCE (C8051F021/3)..........................................................................93 11. COMPARATORS..................................................................................................................95 12. CIP-51 MICROCONTROLLER........................................................................................101 12.1.Instruction Set................................................................................................................102 12.1.1. Instruction and CPU Timing................................................................................102 12.1.2. MOVX Instruction and Program Memory...........................................................102 12.2.Memory Organization ...................................................................................................107 12.2.1. Program Memory .................................................................................................107 12.2.2. Data Memory .......................................................................................................108 12.2.3. General Purpose Registers ...................................................................................108 12 ...
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... Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0])......................................165 17.1.7. External Memory Interface Pin Assignments ......................................................166 17.1.8. Crossbar Pin Assignment Example......................................................................168 17.2.Ports 4 through 7 (C8051F020/2 only)..........................................................................177 17.2.1. Configuring Ports which are not Pinned Out.......................................................177 17.2.2. Configuring the Output Modes of the Port Pins ..................................................177 17 ...
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... C8051F020/1/2/3 18.3.SMBus Transfer Modes.................................................................................................187 18.3.1. Master Transmitter Mode ....................................................................................187 18.3.2. Master Receiver Mode.........................................................................................187 18.3.3. Slave Transmitter Mode.......................................................................................188 18.3.4. Slave Receiver Mode ...........................................................................................188 18.4.SMBus Special Function Registers ...............................................................................189 18.4.1. Control Register ...................................................................................................189 18.4.2. Clock Rate Register .............................................................................................192 18.4.3. Data Register........................................................................................................193 18 ...
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... Pulse Width Modulator Mode ..................................................................258 23.3.Register Descriptions for PCA0 ....................................................................................259 24. JTAG (IEEE 1149.1)............................................................................................................265 24.1.Boundary Scan...............................................................................................................266 24.1.1. EXTEST Instruction ............................................................................................267 24.1.2. SAMPLE Instruction ...........................................................................................267 24.1.3. BYPASS Instruction ............................................................................................267 24.1.4. IDCODE Instruction ............................................................................................267 24.2.Flash Programming Commands ....................................................................................268 24.3.Debug Support...............................................................................................................271 C8051F020/1/2/3 Rev. 1.4 7 ...
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... C8051F020/1/2/3 8 Notes Rev. 1.4 ...
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... Figure 5.11. ADC0 Data Word Example (C8051F020/1) .......................................................52 Figure 5.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register (C8051F020/1) .....53 Figure 5.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register (C8051F020/1) ......53 Figure 5.14. ADC0LTH: ADC0 Less-Than Data High Byte Register (C8051F020/1) ..........53 Figure 5.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register (C8051F020/1) ...........53 Figure 5 ...
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... Figure 7.2. ADC1 Track and Conversion Example Timing ..................................................77 Figure 7.3. ADC1 Equivalent Input Circuit...........................................................................78 Figure 7.4. ADC1CF: ADC1 Configuration Register (C8051F020/1/2/3)............................79 Figure 7.5. AMX1SL: AMUX1 Channel Select Register (C8051F020/1/2/3) .....................79 Figure 7.6. ADC1CN: ADC1 Control Register (C8051F020/1/2/3) .....................................80 Figure 7.7. ADC1: ADC1 Data Word Register .....................................................................81 Figure 7 ...
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... Table 13.1. Reset Electrical Characteristics .........................................................................133 14. OSCILLATORS...................................................................................................................135 Figure 14.1. Oscillator Diagram ............................................................................................135 Figure 14.2. OSCICN: Internal Oscillator Control Register .................................................136 Table 14.1. Internal Oscillator Electrical Characteristics.....................................................136 Figure 14.3. OSCXCN: External Oscillator Control Register...............................................137 15. FLASH MEMORY ..............................................................................................................139 C8051F020/1/2/3 Rev. 1.4 11 ...
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... C8051F020/1/2/3 Table 15.1. FLASH Electrical Characteristics .....................................................................140 Figure 15.1. FLASH Program Memory Map and Security Bytes .........................................141 Figure 15.2. FLACL: FLASH Access Limit .........................................................................142 Figure 15.3. FLSCL: FLASH Memory Control ....................................................................143 Figure 15.4. PSCTL: Program Store Read/Write Control .....................................................144 16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................145 Figure 16 ...
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... Table 21.1. UART1 Modes ..................................................................................................216 Figure 21.2. UART1 Mode 0 Interconnect............................................................................216 Figure 21.3. UART1 Mode 0 Timing Diagram .....................................................................216 Figure 21.4. UART1 Mode 1 Timing Diagram .....................................................................217 Figure 21.5. UART Modes 2 and 3 Timing Diagram............................................................218 Figure 21.6. UART Modes 1, 2, and 3 Interconnect Diagram ..............................................219 C8051F020/1/2/3 Rev. 1.4 13 ...
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... C8051F020/1/2/3 Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................................220 Table 21.2. Oscillator Frequencies for Standard Baud Rates...............................................222 Figure 21.8. SCON1: UART1 Control Register....................................................................223 Figure 21.9. SBUF1: UART1 Data Buffer Register..............................................................224 Figure 21.10. SADDR1: UART1 Slave Address Register ....................................................224 Figure 21 ...
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... Table 24.1. Boundary Data Register Bit Definitions............................................................266 Figure 24.2. DEVICEID: JTAG Device ID Register ............................................................267 Figure 24.3. FLASHCON: JTAG Flash Control Register.....................................................269 Figure 24.4. FLASHADR: JTAG Flash Address Register ....................................................270 Figure 24.5. FLASHDAT: JTAG Flash Data Register..........................................................270 C8051F020/1/2/3 Rev. 1.4 15 ...
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... C8051F020/1/2/3 16 Notes Rev. 1.4 ...
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... Each MCU is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (-45° +85° C). The Port I/Os, /RST, and JTAG pins are tolerant for input signals The C8051F020/2 are available in a 100-pin TQFP package (see block diagrams in Figure 1.1 and Figure 1.3). The C8051F021/3 are available in a 64-pin TQFP package (see block diagrams in Figure 1 ...
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... C8051F020/1/2/3 Figure 1.1. C8051F020 Block Diagram VDD VDD VDD Digital Power DGND DGND DGND AV+ AV+ Analog Power AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset /RST VDD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock ...
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... PCA 1 Timers 0, SFR Bus Timer 3/ RTC C 64kbyte P0, P1, FLASH P2 Latches 256 byte Crossbar RAM r Config. 4kbyte e RAM External Data Memory Bus Bus Control Address Bus Data Bus Rev. 1.4 C8051F020/1/2/3 P0.0 P0 Drv P0 P1.0/AIN1 Drv P1.7/AIN1 P2 Drv P2 P3.0 P3 Drv P3.7 A ADC 8:1 ...
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... C8051F020/1/2/3 Figure 1.3. C8051F022 Block Diagram VDD VDD VDD Digital Power DGND DGND DGND AV+ AV+ Analog Power AGND AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock ...
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... PCA 1 Timers 0, SFR Bus Timer 3/ RTC C 64kbyte P0, P1, FLASH P2 Latches 256 byte Crossbar RAM r Config. 4kbyte e RAM External Data Memory Bus Bus Control Address Bus Data Bus Rev. 1.4 C8051F020/1/2/3 P0.0 P0 Drv P0 P1.0/AIN1 Drv P1.7/AIN1 P2 Drv P2 P3.0 P3 Drv P3.7 A ADC 8:1 ...
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... CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F020 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compati- ble with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The core has all the peripherals included with a standard 8052, including five 16-bit counter/timers, two full- duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and 8/4 byte- wide I/O Ports ...
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... Additional Features The C8051F020 MCU family includes several key enhancements to the CIP-51 core and peripherals to improve over- all performance and ease of use in end applications. The extended interrupt handler provides 22 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller ...
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... The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. The CIP-51 in the C8051F020/1/2/3 MCUs additionally has an on-chip 4k byte RAM block and an external memory interface (EMIF) for accessing off-chip data memory. The on-chip 4k byte block can be addressed over the entire 64k external data memory address range (overlapping 4k boundaries) ...
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... JTAG Debug and Boundary Scan The C8051F020 family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive, full speed, in-circuit debugging using the production part installed in the end application, via the four-pin JTAG interface. The JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing purposes. ...
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... C8051F020/1/2/3 1.4. Programmable Digital I/O and Crossbar The standard 8051 Ports ( and 3) are available on the MCUs. The C8051F020/2 have 4 additional ports ( and 7) for a total of 64 general-purpose port I/O. The Port I/O behave like the standard 8051 with a few enhance- ments. Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the "weak pull-ups" which are normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low-power applications ...
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... Programmable Counter Array The C8051F020 MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with 5 pro- grammable capture/compare modules. The timebase is clocked from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow, an External Clock Input (ECI pin), the system clock, or the external oscillator source divided by 8 ...
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... C8051F022/3 devices include a 10-bit SAR ADC with similar specifications and configuration options. The ADC0 voltage reference is selected between the DAC0 output and an external VREF pin. On C8051F020/2 devices, ADC0 has its own dedicated VREF0 input pin; on C8051F021/3 devices, the ADC0 shares the VREFA input pin with the 8- bit ADC1. The on-chip 15 ppm/° ...
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... Special Function Registers. The ADC1 voltage reference is selected between the analog power supply (AV+) and an external VREF pin. On C8051F020/2 devices, ADC1 has its own dedicated VREF1 input pin; on C8051F021/3 devices, ADC1 shares the VREFA input pin with the 12/10-bit ADC0. User software may put ADC1 into shutdown mode to save power ...
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... DAC output updates to be forced by a software write or a Timer overflow. The DAC voltage reference is supplied via the dedicated VREFD input pin on C8051F020/2 devices or via the internal voltage refer- ence on C8051F021/3 devices. The DACs are especially useful as references for the comparators or offsets for the differential inputs of the ADC ...
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... Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051F020/1/2/3 * CONDITIONS MIN ...
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... C8051F020/1/2/3 3. GLOBAL DC ELECTRICAL CHARACTERISTICS Table 1.1. Global DC Electrical Characteristics -40°C to +85°C, 25 MHz System Clock unless otherwise specified. PARAMETER Analog Supply Voltage Analog Supply Current AV+=2.7 V, Internal REF, ADC, DAC, Comparators all active Analog Supply Current with AV+=2.7 V, Internal REF, ADC, ...
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... When tied low, the internal VDD monitor is disabled. A I/O Bandgap Voltage Reference Output (all devices). DAC Voltage Reference Input (F021/3 only ADC0 and ADC1 Voltage Reference Input ADC0 Voltage Reference Input ADC1 Voltage Reference Input DAC Voltage Reference Input. Rev. 1.4 C8051F020/1/2/3 33 ...
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... C8051F020/1/2/3 Pin Numbers Name F020 F021 F022 F023 AIN0 AIN0 AIN0 AIN0 AIN0 AIN0 AIN0 AIN0 CP0 CP0 CP1 CP1 DAC0 100 64 DAC1 ALE/P0 Table 4.1. Pin Definitions Type Description A In ADC0 Input Channel 0 (See ADC0 Specification for complete description) ...
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... D I/O Port 2.2. See Port Input/Output section for complete description. D I/O Port 2.3. See Port Input/Output section for complete description. D I/O Port 2.4. See Port Input/Output section for complete description. D I/O Port 2.5. See Port Input/Output section for complete description. Rev. 1.4 C8051F020/1/2/3 35 ...
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... C8051F020/1/2/3 Pin Numbers Name F020 F021 F022 F023 A14m/A6/P2 A15m/A7/P2 AD0/D0/P3 AD1/D1/P3 AD2/D2/P3 AD3/D3/P3 AD4/D4/P3 AD5/D5/P3 AD6/D6/P3.6/IE6 48 39 AD7/D7/P3.7/IE7 47 38 P4.0 98 P4.1 97 P4.2 96 P4.3 95 P4.4 94 ALE/P4.5 93 /RD/P4.6 92 /WR/P4.7 91 A8/P5.0 88 A9/P5.1 87 A10/P5 Table 4.1. Pin Definitions Type Description D I/O Port 2.6. See Port Input/Output section for complete description. ...
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... D I/O Port 7.7. See Port Input/Output section for complete description. Table 4.1. Pin Definitions Description Bit 0 External Memory Address bus (Non-multiplexed mode) Port 6.0 See Port Input/Output section for complete description. Bit 0 External Memory Data bus (Non-multiplexed mode) Port 7.0 See Port Input/Output section for complete description. Rev. 1.4 C8051F020/1/2/3 37 ...
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... CP1+ 7 CP0- 8 CP0+ 9 AGND 10 AV+ 11 VREF 12 AGND 13 AV+ 14 VREFD 15 VREF0 16 VREF1 17 AIN0.0 18 AIN0.1 19 AIN0.2 20 AIN0.3 21 AIN0.4 22 AIN0.5 23 AIN0.6 24 AIN0 C8051F020 C8051F022 Rev. 1.4 75 A13m/A5/P6.5 74 A14m/A6/P6.6 73 A15m/A7/P6.7 72 AD0/D0/P7.0 71 AD1/D1/P7.1 70 AD2/D2/P7.2 69 AD3/D3/P7.3 68 AD4/D4/P7.4 67 AD5/D5/P7.5 66 AD6/D6/P7.6 65 AD7/D7/P7.7 64 VDD 63 DGND 62 P0.0 61 P0.1 60 P0.2 59 P0.3 58 P0.4 57 ALE/P0 ...
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... Figure 4.2. TQFP-100 Package Drawing 100 PIN 1 DESIGNATOR Rev. 1.4 C8051F020/1/2/3 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0. 16. 14. 0. 16. 14. ...
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... C8051F020/1/2/3 Figure 4.3. TQFP-64 Pinout Diagram CP1- 1 CP1+ 2 CP0- 3 CP0+ 4 AGND 5 AV+ 6 VREF 7 VREFA 8 AIN0.0 9 AIN0.1 10 AIN0.2 11 AIN0.3 12 AIN0.4 13 AIN0.5 14 AIN0.6 15 AIN0 C8051F021 C8051F023 Rev. 1.4 48 /WR/P0.7 47 AD0/D0/P3.0 46 AD1/D1/P3.1 45 AD2/D2/P3.2 44 AD3/D3/P3.3 43 AD4/D4/P3.4 42 AD5/D5/P3.5 41 VDD 40 DGND 39 AD6/D6/P3.6/IE6 38 AD7/D7/P3.7/IE7 37 A8m/A0/P2.0 36 A9m/A1/P2.1 35 A10m/A2/P2.2 34 A11m/A3/P2.3 33 A12m/A4/P2 ...
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... Figure 4.4. TQFP-64 Package Drawing PIN 1 DESIGNATOR Rev. 1.4 C8051F020/1/2/3 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 - 1.05 b 0.17 0.22 0. 12. 10. 0. 12. 10. ...
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... C8051F020/1/2/3 42 Notes Rev. 1.4 ...
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... ADC0 (12-BIT ADC, C8051F020/1 ONLY) The ADC0 subsystem for the C8051F020/1 consists of a 9-channel, configurable analog multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram in Figure 5.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable under software control via the Special Function Regis- ters shown in Figure 5 ...
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... C8051F020/1 The Temperature Sensor transfer function is shown in Figure 5.2. The output voltage (V the Temperature Sensor is selected by bits AMX0AD3-0 in register AMX0SL; this voltage will be amplified by the PGA according to the user-programmed PGA settings. Figure 5.2. Temperature Sensor Transfer Function (Volts) 1.000 0.900 0.800 ...
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... B. ADC Timing for Internal Trigger Sources Timer 2, Timer 3 Overflow; Write '1' to AD0BUSY (AD0STM[1:0]=00, 01, 11) 1 SAR Clocks Low Power ADC0TM=1 or Convert 1 SAR Clocks Track or ADC0TM=0 Convert Track Convert Convert Track Convert Convert Rev. 1.4 C8051F020/1 46). Low Power Mode Track Low Power Mode Track 45 ...
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... C8051F020/1 5.2.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum settling (or tracking) time is required before an accurate conversion can be performed. This settling time is determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion ...
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... Figure 5.5. AMX0CF: AMUX0 Configuration Register (C8051F020/1) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: AIN67IC: AIN6, AIN7 Input Pair Configuration Bit 0: AIN6 and AIN7 are independent single-ended inputs 1: AIN6, AIN7 are (respectively differential input pair ...
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... C8051F020/1 Figure 5.6. AMX0SL: AMUX0 Channel Select Register (C8051F020/1) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMX0AD3-0: AMX0 Address Bits 0000-1111b: ADC Inputs selected per chart below 0000 0001 0000 AIN0 AIN1 +(AIN0) 0001 ...
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... Figure 5.7. ADC0CF: ADC0 Configuration Register (C8051F020/1) R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in AD0SC4-0, and CLK Table 5 ...
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... C8051F020/1 Figure 5.8. ADC0CN: ADC0 Control Register (C8051F020/1) R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. Bit6: ...
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... Figure 5.9. ADC0H: ADC0 Data Word MSB Register (C8051F020/1) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4 bits of the 12-bit ADC0 Data Word. ...
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... C8051F020/1 Figure 5.11. ADC0 Data Word Example (C8051F020/1) 12-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows: ADC0H[3:0]:ADC0L[7:0], if AD0LJST = 0 (ADC0H[7:4] will be sign-extension of ADC0H.3 for a differential reading, otherwise = 0000b). ADC0H[7:0]:ADC0L[7:4], if AD0LJST = 1 (ADC0L[3:0] = 0000b). Example: ADC0 Data Word Conversion Map, AIN0 Input in Single-Ended Mode ...
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... Figure 5.14. ADC0LTH: ADC0 Less-Than Data High Byte Register (C8051F020/1) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: High byte of ADC0 Less-Than Data Word. Figure 5.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register (C8051F020/1) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low byte of ADC0 Less-Than Data Word. ...
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... C8051F020/1 Figure 5.16. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0x0FFF AD0WINT not affected 0x0201 REF x (512/4096) 0x0200 ADC0LTH:ADC0LTL 0x01FF AD0WINT=1 0x0101 REF x (256/4096) 0x0100 ADC0GTH:ADC0GTL 0x00FF AD0WINT not affected ...
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... ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0xFFFF. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x0100 and > 0xFFFF. (In two’s-complement math, 0xFFFF = -1.) C8051F020/1 Input Voltage ADC Data (AD0 - AD1) Word REF x (2047/2048) 0x07FF 0x0101 ...
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... C8051F020/1 Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0xFFF0 AD0WINT not affected 0x2010 REF x (512/4096) 0x2000 ADC0LTH:ADC0LTL 0x1FF0 AD0WINT=1 0x1010 REF x (256/4096) 0x1000 ADC0GTH:ADC0GTL 0x0FF0 AD0WINT not affected ...
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... AD0LJST = ‘1’, ADC0LTH:ADC0LTL = 0x1000, ADC0GTH:ADC0GTL = 0xFFF0. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x1000 and > 0xFFF0. (Two’s-complement math.) C8051F020/1 Input Voltage ADC Data (AD0 - AD1) Word REF x (2047/2048) 0x7FF0 ...
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... C8051F020/1 Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F020/1) VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient DYNAMIC PERFORMANCE (10 kHz sine-wave input below Full Scale, 100 ksps ...
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... Conversion Modes, and Window Detector are all configurable under software control via the Special Function Regis- ters shown in Figure 6.1. The voltage reference used by ADC0 is selected as described in REFERENCE (C8051F020/2)” on page 91 (C8051F021/3)” on page 93 for C8051F021/3 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1 ...
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C8051F022/3 The Temperature Sensor transfer function is shown in Figure 6.2. The output voltage (V the Temperature Sensor is selected by bits AMX0AD3-0 in register AMX0SL; this voltage will be amplified by the PGA according to the user-programmed PGA settings. ...
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Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates ...
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C8051F022/3 6.2.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum settling (or tracking) time is required before an accurate conversion can be performed. This settling time is ...
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Figure 6.5. AMX0CF: AMUX0 Configuration Register (C8051F022/3) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: AIN67IC: AIN6, AIN7 Input Pair Configuration Bit 0: AIN6 and AIN7 are independent single-ended ...
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C8051F022/3 Figure 6.6. AMX0SL: AMUX0 Channel Select Register (C8051F022/3) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMX0AD3-0: AMX0 Address Bits 0000-1111b: ADC Inputs selected per chart below 0000 ...
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Figure 6.7. ADC0CF: ADC0 Configuration Register (C8051F022/3) R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to ...
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C8051F022/3 Figure 6.8. ADC0CN: ADC0 Control Register (C8051F022/3) R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ...
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Figure 6.9. ADC0H: ADC0 Data Word MSB Register (C8051F022/3) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC Data Word High-Order Bits. For ADLJST = 0: Bits 7-2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits ...
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C8051F022/3 Figure 6.11. ADC0 Data Word Example (C8051F022/3) 10-bit ADC Data Word appears in the ADC Data Word Registers as follows: ADC0H[1:0]:ADC0L[7:0], if ADLJST = 0 (ADC0H[7:2] will be sign-extension of ADC0H.1 for a differential reading, otherwise = 000000b). ADC0H[7:0]:ADC0L[7:6], ...
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ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and ...
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C8051F022/3 Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0x03FF ADWINT not affected 0x0201 REF x (512/1024) 0x0200 ADC0LTH:ADC0LTL 0x01FF ADWINT=1 0x0101 REF x (256/1024) 0x0100 ...
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Figure 6.17. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential Data Input Voltage ADC Data (AD0 - AD1) Word REF x (511/512) 0x01FF ADWINT not affected 0x0101 REF x (256/512) 0x0100 ADC0LTH:ADC0LTL 0x00FF ADWINT=1 0x0000 REF x (-1/512) 0xFFFF ADC0GTH:ADC0GTL ...
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C8051F022/3 Figure 6.18. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0xFFC0 ADWINT not affected 0x8040 REF x (512/1024) 0x8000 ADC0LTH:ADC0LTL 0x7FC0 ADWINT=1 0x4040 REF x (256/1024) 0x4000 ...
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Figure 6.19. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data Input Voltage ADC Data (AD0 - AD1) Word REF x (511/512) 0x7FC0 ADWINT not affected 0x2040 REF x (128/512) 0x2000 ADC0LTH:ADC0LTL 0x1FC0 ADWINT=1 0x0000 REF x (-1/512) 0xFFC0 ADC0GTH:ADC0GTL ...
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C8051F022/3 Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F022/3) VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale ...
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... ADC1 (8-BIT ADC) The ADC1 subsystem for the C8051F020/1/2/3 consists of an 8-channel, configurable analog multiplexer (AMUX1), a programmable gain amplifier (PGA1), and a 500 ksps, 8-bit successive-approximation-register ADC with inte- grated track-and-hold (see block diagram in Figure 7.1). The AMUX1, PGA1, and Data Conversion Modes, are all configurable under software control via the Special Function Registers shown in Figure 7 ...
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... C8051F020/1/2/3 7.2. ADC1 Modes of Operation ADC1 has a maximum conversion speed of 500 ksps. The ADC1 conversion clock (SAR1 clock divided version of the system clock, determined by the AD1SC bits in the ADC1CF register (system clock divided by (AD1SC + 1) for 0 AD1SC 31). The maximum ADC1 conversion clock is 6 MHz. ...
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... Track or Convert B. ADC Timing for Internal Trigger Source Write '1' to AD1BUSY, Timer 3 Overflow, Timer 2 Overflow, Write '1' to AD0BUSY (AD1CM[2:0]=000, 001, 011, 1xx) SAR1 Clocks Low Power AD1TM=1 or Convert SAR1 Clocks Track or AD1TM=0 Convert C8051F020/1/2 Track Convert Low Power Mode Convert 1 ...
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... C8051F020/1/2/3 7.2.3. Settling Time Requirements When the ADC1 input configuration is changed (i.e., a different MUX or PGA selection), a minimum settling (or tracking) time is required before an accurate conversion can be performed. This settling time is determined by the ADC1 MUX resistance, the ADC1 sampling capacitance, any external source resistance, and the accuracy required for the conversion ...
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... CLK SAR1 Bit2: UNUSED. Read = 0b. Write = don’t care. Bits1-0: AMP1GN1-0: ADC1 Internal Amplifier Gain (PGA) 00: Gain = 0.5 01: Gain = 1 10: Gain = 2 11: Gain = 4 Figure 7.5. AMX1SL: AMUX1 Channel Select Register (C8051F020/1/2/3) R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b; Write = don’t care ...
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... C8051F020/1/2/3 Figure 7.6. ADC1CN: ADC1 Control Register (C8051F020/1/2/3) R/W R/W R/W AD1EN AD1TM AD1INT AD1BUSY AD1CM2 AD1CM1 Bit7 Bit6 Bit5 Bit7: AD1EN: ADC1 Enable Bit. 0: ADC1 Disabled. ADC1 is in low-power shutdown. 1: ADC1 Enabled. ADC1 is active and ready for data conversions. Bit6: AD1TM: ADC1 Track Mode Bit ...
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... Example: ADC1 Data Word Conversion Map, AIN1.0 Input (AMX1SL = 0x00) AIN1.0-AGND (Volts) VREF * (255/256) VREF / 2 VREF * (127/256) 0 Gain -------------- - Code = Vin VREF R/W R/W R/W Bit4 Bit3 Bit2 ADC1 0xFF 0x80 0x7F 0x00 256 Rev. 1.4 C8051F020/1/2/3 R/W R/W Reset Value 00000000 Bit1 Bit0 SFR Address: 0x9C 81 ...
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... C8051F020/1/2/3 Table 7.1. ADC1 Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, VREF1 = 2.40 V (REFBE=0), PGA1 = 1, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient DYNAMIC PERFORMANCE (10 kHz sine-wave input below Full Scale, 500 ksps ...
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... DAC output is maintained in a high-impedance state, and the DAC supply current falls to 1 µA or less. The volt- age reference for each DAC is supplied at the VREFD pin (C8051F020/2 devices) or the VREF pin (C8051F021/3 devices). Note that the VREF pin on C8051F021/3 devices may be driven by the internal voltage reference or an external source ...
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... C8051F020/1/2/3 8.1.1. Update Output On-Demand In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” write to the high-byte of the DAC0 data register (DAC0H). It’s important to note that writes to DAC0L are held, and have no effect on the DAC0 output until a write to DAC0H takes place. If writing a full 12-bit word to the DAC data registers, the 12-bit data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers ...
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... Bit5 Bits7-0: DAC0 Data Word Most Significant Byte. Figure 8.3. DAC0L: DAC0 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Least Significant Byte. C8051F020/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
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... C8051F020/1/2/3 Figure 8.4. DAC0CN: DAC0 Control Register R/W R/W R/W DAC0EN - - Bit7 Bit6 Bit5 Bit7: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. 1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational. Bits6-5: UNUSED. Read = 00b; Write = don’t care. ...
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... Bit5 Bits7-0: DAC1 Data Word Most Significant Byte. Figure 8.6. DAC1L: DAC1 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Least Significant Byte. C8051F020/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
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... C8051F020/1/2/3 Figure 8.7. DAC1CN: DAC1 Control Register R/W R/W R/W DAC1EN - - Bit7 Bit6 Bit5 Bit7: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. 1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational. Bits6-5: UNUSED. Read = 00b; Write = don’t care. ...
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... Output Voltage Swing Startup Time ANALOG OUTPUTS Load Regulation I L POWER CONSUMPTION (each DAC) Power Supply Current (AV+ sup- Data Word = 0x7FF plied to DAC) CONDITIONS = 0.01mA to 0.3mA at code 0xFFF Rev. 1.4 C8051F020/1/2/3 MIN TYP MAX UNITS 12 bits ±2 LSB ±1 LSB 250 µVrms ...
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... C8051F020/1/2/3 90 Notes Rev. 1.4 ...
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... VOLTAGE REFERENCE (C8051F020/2) The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage reference input pins allow each ADC and the two DACs to reference an external voltage reference or the on-chip voltage refer- ence output. ADC0 may also reference the DAC0 output internally, and ADC1 may reference the analog power sup- ply voltage, via the VREF multiplexers shown in Figure 9.1. The internal voltage reference circuit consists ppm/° ...
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... C8051F020/1/2/3 The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Multiplexer and PGA” on page 43 for C8051F020/1 devices, or page 59 for C8051F022/3 devices). The TEMPE bit within REF0CN enables and disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any A/D measurements performed on the sensor while disabled result in undefined data ...
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... Figure 10.1. Voltage Reference Functional Block Diagram VDD External R1 Voltage Reference Circuit DGND 4.7F 0.1F Recommended Bypass Capacitors REF0CN AV VREFA 0 1 DAC0 Ref DAC1 VREF x2 REFBE Rev. 1.4 C8051F020/1/2/3 ADC1 Ref ADC0 Ref BIASE Bias to EN ADCs, DACs 1.2V Band-Gap 93 ...
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... C8051F020/1/2/3 The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Multiplexer and PGA” on page 43 for C8051F020/1 devices, or page 59 for C8051F022/3 devices). The TEMPE bit within REF0CN enables and disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any A/D measurements performed on the sensor while disabled result in undefined data ...
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... CP0HYP1 CP0HYP0 Reset CP0HYN1 Decision CP0HYN0 + D - (SYNCHRONIZER) AGND CP1EN CP1OUT CP1RIF AV+ CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 + D - (SYNCHRONIZER) AGND Rev. 1.4 C8051F020/1/2/3 for Crossbar and port initialization Tree Crossbar SET SET CLR CLR Interrupt Handler Crossbar SET SET CLR CLR Interrupt Handler ...
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... C8051F020/1/2/3 Figure 11.2. Comparator Hysteresis Plot CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled to logic 0. Comparator0 can also be programmed as a reset source; for details, see Section Reset” on page 129. ...
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... CP0HYN1-0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 2 mV. 10: Negative Hysteresis = 4 mV. 11: Negative Hysteresis = 10 mV. R/W R/W R/W CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit4 Bit3 Bit2 Rev. 1.4 C8051F020/1/2/3 R/W R/W Reset Value Bit1 Bit0 SFR Address: 0x9E 97 ...
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... C8051F020/1/2/3 Figure 11.4. CPT1CN: Comparator1 Control Register R/W R/W R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1-. 1: Voltage on CP1+ > CP1-. Bit5: CP1RIF: Comparator1 Rising-Edge Interrupt Flag. ...
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... CPnHYN1 Negative Hysteresis 4 CPnHYN1 Inverting or Non-Inverting Input Voltage Range Input Capacitance Input Bias Current Input Offset Voltage POWER SUPPLY Power-up Time CPnEN from Power Supply Rejection Supply Current Operating Mode (each comparator C8051F020/1/2/3 CONDITIONS MIN -0.25 -5 -10 Rev. 1.4 TYP MAX ...
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... C8051F020/1/2/3 100 Notes Rev. 1.4 ...
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... REGISTER DATA BUS BUFFER D8 SFR BUS D8 D8 INTERFACE D8 MEMORY A16 INTERFACE PIPELINE D8 INTERRUPT INTERFACE D8 D8 Rev. 1.4 C8051F020/1/2/3 and Section 21), 256 bytes of internal Section 24), and STACK POINTER SRAM (256 X 8) SFR_ADDRESS SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA MEM_ADDRESS MEM_CONTROL MEM_WRITE_DATA MEM_READ_DATA SYSTEM_IRQs EMULATION_IRQ 101 ...
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... C8051F020/1/2/3 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to exe- cute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instruc- tions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...
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... ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A Section “16. EXTERNAL DATA MEMORY INTER- for details. ARITHMETIC OPERATIONS LOGICAL OPERATIONS Rev. 1.4 C8051F020/1/2/3 Clock Bytes Cycles ...
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... C8051F020/1/2/3 Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A ...
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... Compare immediate to Register and jump if not equal CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation C8051F020/1/2/3 PROGRAM BRANCHING Rev. 1.4 Clock Bytes Cycles ...
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... C8051F020/1/2/3 Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. ...
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... Registers 0x00 EXTERNAL DATA ADDRESS SPACE 0xFFFF Off-chip XRAM space 0x1000 0x0FFF XRAM - 4096 Bytes (accessable using MOVX instruction) 0x0000 for further details. Rev. 1.4 C8051F020/1/2/3 Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) Sec- 107 ...
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... C8051F020/1/2/3 12.2.2. Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...
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... ADC0CF ADC1CF AMX1SL EMI0CF P0MDOUT P1MDOUT P2MDOUT P3MDOUT SPI0DAT ADC1 TMR3L TL0 TL1 TH0 DPL DPH P4† 2(A) 3(B) 4(C) Rev. 1.4 C8051F020/1/2/3 WDTCN TH4 EIP1 EIP2 RSTSRC RCAP4H EIE1 EIE2 DAC1L DAC1H DAC1CN TH2 SMB0CR ADC0LTL ADC0LTH P1MDIN ADC0L ADC0H P74OUT† ...
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... C8051F020/1/2/3 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description ADC0LTH 0xC7 ADC0 Less-Than High ADC0LTL 0xC6 ADC0 Less-Than Low ADC1CF 0xAB ADC1 Analog Multiplexer Configuration ADC1CN 0xAA ADC1 Control ADC1 ...
Page 111
... SMBus Clock Rate SMB0DAT 0xC2 SMBus Data SMB0STA 0xC1 SMBus Status SP 0x81 Stack Pointer C8051F020/1/2/3 page 92†, page 94†† Rev. 1.4 Page No. page 181† page 181† page 179† page 259 page 263 page 263 page 263 ...
Page 112
... Port I/O Crossbar Control 2 0x97, 0xA2, 0xB3, 0xB4, Reserved 0xCE, 0xDF * Refers to a register in the C8051F020/1 only. ** Refers to a register in the C8051F022/3 only. † Refers to a register in the C8051F020/2 only. †† Refers to a register in the C8051F021/3 only. 112 Rev. 1.4 Page No. page 201 ...
Page 113
... R/W R/W Bit4 Bit3 Bit2 R/W R/W R/W Bit4 Bit3 Bit2 R/W R/W R/W Bit4 Bit3 Bit2 Rev. 1.4 C8051F020/1/2/3 R/W R/W Reset Value 00000111 Bit1 Bit0 SFR Address: 0x81 R/W R/W Reset Value 00000000 Bit1 Bit0 SFR Address: 0x82 R/W ...
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... C8051F020/1/2/3 Figure 12.6. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtrac- tion cleared all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition borrow from (subtraction) the high order nibble ...
Page 115
... ACC.3 ACC.2 ACC.1 Bit4 Bit3 Bit2 Figure 12. Register R/W R/W R/W B.4 B.3 B.2 Bit4 Bit3 Bit2 Rev. 1.4 C8051F020/1/2/3 R/W R/W Reset Value ACC.0 00000000 Bit1 Bit0 SFR Address: 0xE0 (bit addressable) R/W R/W Reset Value B.1 B.0 00000000 Bit1 ...
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... C8051F020/1/2/3 12.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the spe- cific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR ...
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... Timer 3 Overflow 0x0073 ADC0 End of Conversion 0x007B Timer 4 Overflow 0x0083 ADC1 End of Conversion 0x008B External Interrupt 6 0x0093 External Interrupt 7 0x009B UART1 0x00A3 External Crystal OSC Ready 0x00AB C8051F020/1/2/3 Priority Pending Flag Order Top None N/A N/A 0 IE0 (TCON. TF0 (TCON. IE1 (TCON. TF1 (TCON ...
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... C8051F020/1/2/3 12.3.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority inter- rupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority level. Low priority is the default ...
Page 119
... Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag (TCON.5). Bit0: EX0: Enable External Interrupt 0. This bit sets the masking of external interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 pin. C8051F020/1/2/3 R/W R/W R/W R/W ES0 ET1 ...
Page 120
... C8051F020/1/2/3 Figure 12.10. IP: Interrupt Priority R/W R/W R PT2 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt priority determined by default priority order. 1: Timer 2 interrupts set to high priority level. ...
Page 121
... This bit sets the masking of SPI0 interrupt. 0: Disable all SPI0 interrupts. 1: Enable Interrupt requests generated by the SPIF flag (SPI0CN.7). R/W R/W R/W ECP0F EPCA0 EWADC0 ESMB0 Bit4 Bit3 Bit2 Rev. 1.4 C8051F020/1/2/3 R/W R/W Reset Value ESPI0 00000000 Bit1 Bit0 SFR Address: 0xE6 121 ...
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... C8051F020/1/2/3 Figure 12.12. EIE2: Extended Interrupt Enable 2 R/W R/W R/W EXVLD ES1 EX7 Bit7 Bit6 Bit5 Bit7: EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt. This bit sets the masking of the XTLVLD interrupt. 0: Disable XTLVLD interrupt. 1: Enable interrupt requests generated by the XTLVLD flag (OSCXCN.7) Bit6: ES1: Enable UART1 Interrupt ...
Page 123
... This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. R/W R/W R/W PCP0F PPCA0 PWADC0 PSMB0 Bit4 Bit3 Bit2 Rev. 1.4 C8051F020/1/2/3 R/W R/W Reset Value PSPI0 00000000 Bit1 Bit0 SFR Address: 0xF6 123 ...
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... C8051F020/1/2/3 Figure 12.14. EIP2: Extended Interrupt Priority 2 R/W R/W R/W PXVLD EP1 PX7 Bit7 Bit6 Bit5 Bit7: PXVLD: External Clock Source Valid (XTLVLD) Interrupt Priority Control. This bit sets the priority of the XTLVLD interrupt. 0: XTLVLD interrupt set to low priority level. 1: XTLVLD interrupt set to high priority level. ...
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... If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU put to sleep for longer than the MCD timeout of 100 µs. C8051F020/1/2/3 for more information on the use and configuration of Rev ...
Page 126
... C8051F020/1/2/3 Figure 12.15. PCON: Power Control R/W R/W R/W SMOD0 SSTAT0 Reserved Bit7 Bit6 Bit5 Bit7: SMOD0: UART0 Baud Rate Doubler Enable. This bit enables/disables the divide-by-two function of the UART0 baud rate logic for configurations described in the UART0 section. 0: UART0 baud rate divide-by-two enabled. ...
Page 127
... Figure 13.1. Reset Sources VDD Supply Monitor Supply + Reset - Timeout (CP0 reset enable) Missing WDT Clock Detector (one- shot PRE System Software Reset Clock CIP-51 Microcontroller Clock Select System Reset Core Extended Interrupt Handler Rev. 1.4 C8051F020/1/2/3 /RST (wired-OR) Reset Funnel 127 ...
Page 128
... C8051F020/1/2/3 13.1. Power-on Reset The C8051F020/1/2/3 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the V level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 for the Elec- RST trical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end of the 100 ms VDD Monitor timeout in order to allow the VDD supply to stabilize ...
Page 129
... The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN) shown in Figure 13.3. Section “11. COMPARATORS” on page 95) prior to writing to C0RSEF to Decoder” on page 163. Note that the Crossbar must be configured for the Rev. 1.4 C8051F020/1/2/3 13.1. “17.1. Ports 0 129 ...
Page 130
... C8051F020/1/2/3 13.8.1. Enable/Reset WDT The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's application soft- ware should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. The WDT is enabled and reset as a result of any system reset. ...
Page 131
... Reading the WDTCN.[4] bit indicates the Watchdog Timer Status. 0: WDT is inactive 1: WDT is active Bits2-0: Watchdog Timeout Interval Bits The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must be set to 0. C8051F020/1/2/3 R/W R/W R/W R/W Bit4 Bit3 ...
Page 132
... C8051F020/1/2/3 Figure 13.4. RSTSRC: Reset Source Register R R/W R/W - CNVRSEF C0RSEF Bit7 Bit6 Bit5 (Note: Do not use read-modify-write operations on this register.) Bit7: Reserved. Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag Write: 0: CNVSTR is not a reset source. 1: CNVSTR is a reset source (active low). ...
Page 133
... Time from last system clock to reset Missing Clock Detector Timeout CONDITIONS MIN VDD - 0.7 = 8.5 mA, VDD = 2 3.6 V 0.7 x VDD /RST = 0.0 V 1.0 1.0 2. threshold RST 100 initiation Rev. 1.4 C8051F020/1/2/3 TYP MAX UNITS V 0 0.3 x VDD 50 µ 2.55 2. 100 120 ms 220 500 µs ...
Page 134
... C8051F020/1/2/3 134 Notes Rev. 1.4 ...
Page 135
... CMOS clock can also provide the system clock; in this configuration, the XTAL1 pin is used as the CMOS clock input. The XTAL1 and XTAL2 pins are NOT 5V tolerant. Figure 14.1. Oscillator Diagram opt. 2 AV+ opt. 4 opt. 3 XTAL1 XTAL1 XTAL1 XTAL2 C8051F020/1/2/3 OSCICN VDD EN Internal Clock Generator AV+ opt. 1 XTAL1 Input OSC ...
Page 136
... C8051F020/1/2/3 Figure 14.2. OSCICN: Internal Oscillator Control Register R/W R/W R/W MSCLKE - - Bit7 Bit6 Bit5 Bit7: MSCLKE: Missing Clock Enable Bit 0: Missing Clock Detector Disabled 1: Missing Clock Detector Enabled; reset triggered if clock is missing for more than 100 µs Bits6-5: UNUSED. Read = 00b, Write = don't care ...
Page 137
... R = Pull-up resistor value in k C MODE (Circuit from Figure 14.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired AV+), where f = frequency of oscillation in MHz C = capacitor value on XTAL1, XTAL2 pins in pF AV+ = Analog Power Supply on MCU in volts C8051F020/1/2/3 R/W R/W R/W R/W - XFCN2 ...
Page 138
... C8051F020/1/2/3 14.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be as shown in Figure 14.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crys- tal column of the table in Figure 14.3 (OSCXCN register). For example, an 11.0592 MHz crystal requires an XFCN setting of 111b ...
Page 139
... FLASH MEMORY The C8051F020/1/2/3 family includes 64k + 128 bytes of on-chip, reprogrammable FLASH memory for program code and non-volatile data storage. The FLASH memory can be programmed in-system, a single byte at a time, through the JTAG interface or by software. Once cleared to logic 0, a FLASH bit must be erased to set it back to logic 1. The bytes would typically be erased (set to 0xFF) before being reprogrammed. FLASH write and erase oper- ations are automatically timed by hardware for proper execution ...
Page 140
... C8051F020/1/2/3 Write/Erase timing is automatically controlled by hardware. Note that code execution in the 8051 is stalled while the FLASH is being programmed or erased. Interrupts that are posted during a FLASH write or erase operation are held pending until the FLASH operation has completed, at which time they are serviced by the CPU in priority order. ...
Page 141
... JTAG erasure, only that page (including the security bytes) will be erased. The FLASH Access Limit security feature (see Figure 15.1) protects proprietary program code and data from being read by software running on the C8051F020/1/2/3. This feature provides support for OEMs that wish to program the C8051F020/1/2/3 SFLE = 0 ...
Page 142
... C8051F020/1/2/3 MCU with proprietary value-added firmware before distribution. The value-added firmware can be protected while allowing additional code to be programmed in remaining program memory space later. The Software Read Limit (SRL 16-bit address that establishes two logical partitions in the program memory space. The first is an upper partition consisting of all the program memory locations at or above the SRL address, and the second is a lower partition consisting of all the program memory locations starting at 0x0000 up to (but exclud- ing) the SRL address ...
Page 143
... This bit must be set to allow FLASH writes from user software. 0: FLASH writes disabled. 1: FLASH writes enabled. R/W R/W R/W Reserved Reserved Reserved Reserved Bit4 Bit3 Bit2 Rev. 1.4 C8051F020/1/2/3 R/W R/W Reset Value FLWE 10000000 Bit1 Bit0 SFR Address: 0xB6 143 ...
Page 144
... C8051F020/1/2/3 Figure 15.4. PSCTL: Program Store Read/Write Control R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b, Write = don't care. Bit2: SFLE: Scratchpad FLASH Memory Access Enable. When this bit is set, FLASH reads and writes from user software are directed to the 128-byte Scratch- pad FLASH sector ...
Page 145
... EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM The C8051F020/1/2/3 MCUs include 4k bytes of on-chip RAM mapped into the external data memory space (XRAM), as well as an External Data Memory Interface which can be used to access off-chip memories and memory- mapped devices connected to the GPIO ports. The external memory space may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using ...
Page 146
... Mode bits are located in the EMI0CF register shown in Figure 16.2. 16.3. Port Selection and Configuration The External Memory Interface can appear on Ports and 0 (C8051F020/1/2/3 devices Ports and 4 (C8051F020/2 devices only), depending on the state of the PRTSEL bit (EMI0CF.5). If the lower Ports are selected, the EMIFLE bit (XBR2.1) must be set to a ‘ ...
Page 147
... PGSEL4 PGSEL3 PGSEL2 PGSEL1 Bit4 Bit3 Bit2 R/W R/W R/W EMD2 EMD1 EMD0 EALE1 Bit4 Bit3 Bit2 Rev. 1.4 C8051F020/1/2/3 R/W R/W Reset Value PGSEL0 00000000 Bit1 Bit0 SFR Address: 0xAF R/W R/W Reset Value EALE0 00000011 Bit1 Bit0 SFR Address: ...
Page 148
... C8051F020/1/2/3 16.4. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 16.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address ...
Page 149
... In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 16.4. See mation about Non-multiplexed operation. Figure 16.4. Non-multiplexed Configuration Example A[15: D[7:0] F /WR /RD C8051F020/1/2/3 Section “16.6.1. Non-multiplexed Mode” on page 153 ADDRESS BUS DATA BUS Rev. 1.4 for more infor- A[15:0] 64K X 8 SRAM ...
Page 150
... C8051F020/1/2/3 16.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 16.5, based on the EMIF Mode bits in the EMI0CF register (Figure 16.2). These modes are summarized below. More information about the different modes can be found in Section “ ...
Page 151
... SYSCLKs). The programmable setup and hold times default to the maximum delay set- tings after a reset. Table 16.1 lists the AC parameters for the External Memory Interface, and Figure 16.7 through Figure 16.11 show the timing diagrams for the different External Memory Interface modes and MOVX operations C8051F020/1/2/3 Rev. 1.4 151 ...
Page 152
... C8051F020/1/2/3 . Figure 16.6. EMI0TC: External Memory Timing Control R/W R/W R/W EAS1 EAS0 EWR3 Bit7 Bit6 Bit5 Bits7-6: EAS1-0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK cycle. 10: Address setup time = 2 SYSCLK cycles. 11: Address setup time = 3 SYSCLK cycles. ...
Page 153
... EMIF WRITE DATA T WDS T T ACS ACW Nonmuxed 16-bit READ EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL EMIF READ DATA T RDS T T ACS ACW Rev. 1.4 C8051F020/1/2/3 P1/P5 P2/P6 P3/P7 T WDH T ACH P0.7/P4.7 P0.6/P4.6 P1/P5 P2/P6 P3/P7 T RDH T ACH P0.6/P4.6 P0 ...
Page 154
... C8051F020/1/2/3 16.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing ADDR[15:8] ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 154 Nonmuxed 8-bit WRITE without Bank Select ...
Page 155
... WDS T T ACS ACW Nonmuxed 8-bit READ with Bank Select EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from EMIF READ DATA T RDS T T ACS ACW Rev. 1.4 C8051F020/1/2/3 P1/P5 P2/P6 P3/P7 T WDH T ACH P0.7/P4.7 P0.6/P4.6 P1/P5 P2/P6 P3/P7 T RDH T ACH P0 ...
Page 156
... C8051F020/1/2/3 16.6.2. Multiplexed Mode 16.6.2.1. 16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. Figure 16.10. Multiplexed 16-bit MOVX Timing ADDR[15:8] P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/P7 T ALEH ALE P0.5/P4.5 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/P7 ...
Page 157
... P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] P3/ ALEH ALE P0.5/P4.5 /RD P0.6/P4.6 /WR P0.7/P4.7 C8051F020/1/2/3 Muxed 8-bit WRITE Without Bank Select P2/P6 EMIF WRITE DATA T ALEL T WDS T T ACS ACW Muxed 8-bit READ Without Bank Select P2/P6 EMIF READ DATA T T ALEL ...
Page 158
... C8051F020/1/2/3 16.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. Figure 16.12. Multiplexed 8-bit MOVX with Bank Select Timing ADDR[15:8] P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/ ALEH ALE P0.5/P4.5 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/ ALEH ALE P0.5/P4.5 /RD P0 ...
Page 159
... ALEH T Address Latch Enable Low Time ALEL T Write Data Setup Time WDS T Write Data Hold Time WDH T Read Data Setup Time RDS T Read Data Hold Time RDH C8051F020/1/2/3 MIN MAX 40 0 3*T 1*T 16*T SYSCLK 0 3*T 1*T 4*T SYSCLK 1*T 4*T ...
Page 160
... C8051F020/1/2/3 160 Notes Rev. 1.4 ...
Page 161
... The C8051F020/1/2/3 are fully integrated mixed-signal System on a Chip MCUs with 64 digital I/O pins (C8051F020/ digital I/O pins (C8051F021/3), organized as 8-bit Ports. The lower ports: P0, P1, P2, and P3, are both bit- and byte-addressable through their corresponding Port Data registers. The upper ports: P4, P5, P6, and P7 are byte-addressable ...
Page 162
... C8051F020/1/2/3 The C8051F020/1/2/3 devices have a wide array of digital resources which are available through the four lower I/O Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin or can be controlled by a digital peripheral or function (like UART0 or /INT1 for example), as shown in Figure 17.2. ...
Page 163
... T2EX T4 T4EX /SYSCLK CNVSTR AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr Muxed Data/Non-muxed Data Rev. 1.4 C8051F020/1/2/3 P3 Crossbar Register Bits UART0EN: XBR0.2 SPI0EN: XBR0.1 SMB0EN: XBR0.0 UART1EN: XBR2.2 PCA0ME: XBR0.[5:3] ECI0E: XBR0.6 CP0E: XBR0.7 CP1E: XBR1.0 T0E: XBR1.1 INT0E: XBR1.2 T1E: XBR1 ...
Page 164
... C8051F020/1/2 Port pin without assigning RX0 as well. Each combination of enabled peripherals results in a unique device pin- out. All Port pins on Ports 0 through 3 that are not allocated by the Crossbar can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the associated Port Data registers (See Figure 17.10, Figure 17.12, Figure 17.15, and Figure 17 ...
Page 165
... Port pin as an Analog Input in order to use input to the ADC1 MUX; however strongly rec- ommended. See Section “7. ADC1 (8-Bit ADC)” on page 75 Section “12.3. Interrupt Handler” on page 116 for more information about ADC1. Rev. 1.4 C8051F020/1/2/3 for more information about 165 ...
Page 166
... C8051F020/1/2/3 17.1.7. External Memory Interface Pin Assignments If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.1) should be set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and if the External Mem- ory Interface is in Multiplexed mode, P0.5 (ALE). Figure 17.4 shows an example Crossbar Decode Table with EMIFLE=1 and the EMIF in Multiplexed mode ...
Page 167
... CNVSTR AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr Muxed Data/Non-muxed Data Rev. 1.4 C8051F020/1/2/3 P3 Crossbar Register Bits UART0EN: XBR0.2 SPI0EN: XBR0.1 SMB0EN: XBR0.0 UART1EN: XBR2.2 PCA0ME: XBR0.[5:3] ECI0E: XBR0.6 CP0E: XBR0 ...
Page 168
... C8051F020/1/2/3 17.1.8. Crossbar Pin Assignment Example In this example (Figure 17.6), we configure the Crossbar to allocate Port pins for UART0, the SMBus, UART1, /INT0, and /INT1 (8 pins total). Additionally, we configure the External Memory Interface to operate in Multiplexed mode and to appear on the Low ports. Further, we configure P1.2, P1.3, and P1.4 for Analog Input mode so that the voltages at these pins can be measured by ADC1 ...
Page 169
... Muxed Data/Non-muxed Data Rev. 1.4 C8051F020/1/2/3 P3 Crossbar Register Bits 1 2 ...
Page 170
... C8051F020/1/2/3 Figure 17.7. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP0E ECI0E Bit7 Bit6 Bit5 Bit7: CP0E: Comparator 0 Output Enable Bit. 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. Bit6: ECI0E: PCA0 External Counter Input Enable Bit. 0: PCA0 External Counter Input unavailable at Port pin. ...
Page 171
... T0 routed to Port pin. Bit0: CP1E: CP1 Output Enable Bit. 0: CP1 unavailable at Port pin. 1: CP1 routed to Port pin. R/W R/W R/W INT1E T1E INT0E Bit4 Bit3 Bit2 Rev. 1.4 C8051F020/1/2/3 R/W R/W Reset Value T0E CP1E 00000000 Bit1 Bit0 SFR Address: 0xE2 171 ...
Page 172
... C8051F020/1/2/3 Figure 17.9. XBR2: Port I/O Crossbar Register 2 R/W R/W R/W WEAKPUD XBARE - Bit7 Bit6 Bit5 Bit7: WEAKPUD: Weak Pull-Up Disable Bit. 0: Weak pull-ups globally enabled. 1: Weak pull-ups globally disabled. Bit6: XBARE: Crossbar Enable Bit. 0: Crossbar disabled. All pins on Ports and 3, are forced to Input mode. ...
Page 173
... Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always configured as Open-Drain when they appear on Port pins. C8051F020/1/2/3 R/W R/W R/W R/W P0 ...
Page 174
... C8051F020/1/2/3 Figure 17.12. P1: Port1 Data Register R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7-0: P1.[7:0]: Port1 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers) 0: Logic Low Output. 1: Logic High Output (open if corresponding P1MDOUT.n bit = 0). ...
Page 175
... Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always configured as Open-Drain when they appear on Port pins. C8051F020/1/2/3 R/W R/W R/W R/W ...
Page 176
... C8051F020/1/2/3 Figure 17.17. P3: Port3 Data Register R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits7-0: P3.[7:0]: Port3 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers) 0: Logic Low Output. 1: Logic High Output (open if corresponding P3MDOUT.n bit = 0). ...
Page 177
... Bits1-0: UNUSED. Read = 00b, Write = don’t care. 17.2. Ports 4 through 7 (C8051F020/2 only) All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the associated Port Data registers (See Figure 17.21, Figure 17.22, Figure 17.23, and Figure 17.24), a set of SFRs which are byte-addressable ...
Page 178
... C8051F020/1/2/3 Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to assume a high- impedance state. The Open-Drain configuration is useful to prevent contention between devices in systems where the Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire. ...
Page 179
... Bit1: P4H: Port4 Output Mode High Nibble Bit. 0: P4.[7:4] configured as Open-Drain. 1: P4.[7:4] configured as Push-Pull. Bit0: P4L: Port4 Output Mode Low Nibble Bit. 0: P4.[3:0] configured as Open-Drain. 1: P4.[3:0] configured as Push-Pull. C8051F020/1/2/3 R/W R/W R/W R/W P6L P5H P5L P4H ...
Page 180
... C8051F020/1/2/3 Figure 17.21. P4: Port4 Data Register R/W R/W R/W P4.7 P4.6 P4.5 Bit7 Bit6 Bit5 Bits7-0: P4.[7:0]: Port4 Output Latch Bits. Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20. Read - Returns states of I/O pins. ...
Page 181
... Read - Returns states of I/O pins. 0: P7.n pin is logic low. 1: P7.n pin is logic high. Note: P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode D[7:0] in Non-multiplexed mode). See FACE AND ON-CHIP XRAM” on page 145 Interface. C8051F020/1/2/3 R/W R/W R/W R/W P6.4 P6.3 P6.2 P6 ...
Page 182
... C8051F020/1/2/3 182 Notes Rev. 1.4 ...
Page 183
... C BUS (SMBUS0 serial bus. Reads and writes to the interface by the Section 18.4 on page SMB0CR Clock Divide SYSCLK Logic FILTER SCL Control SDA Data Path Control Control 8 SMB0DAT FILTER Read Write to SMB0DAT SMB0DAT Rev. 1.4 C8051F020/1/2/3 189. SCL Port I SDA N 183 ...
Page 184
... C8051F020/1/2/3 Figure 18.2 shows a typical SMBus configuration. The SMBus0 interface will work at any voltage between 3.0 V and 5.0 V and different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar circuit ...
Page 185
... A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. C8051F020/1/2/3 R/W D7 ACK ...
Page 186
... C8051F020/1/2/3 18.2.3. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the mas- ter cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than “timeout” condi- tion ...
Page 187
... Received by SMBus Interface Transmitted by SMBus Interface A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address R A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address Rev. 1.4 C8051F020/1/2 Interrupt N P Interrupt 187 ...
Page 188
... C8051F020/1/2/3 18.3.3. Slave Transmitter Mode Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START followed by data byte containing the slave address and direction bit. If the received slave address matches the address held in register SMB0ADR, the SMBus0 interface generates an ACK. SMBus0 will also ACK if the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the data direction bit (R/W) will be logic 1 to indicate a " ...
Page 189
... SDA sent during acknowledge cycle. After the transmission of a byte in slave mode, the slave can be tempo- rarily removed from the bus by clearing the AA flag. The slave's own address and general call address will be ignored. To resume operation on the bus, the AA flag must be reset to logic 1 to allow the slave's address to be recog- nized. C8051F020/1/2/3 Rev. 1.4 189 ...
Page 190
... C8051F020/1/2/3 Setting the SMBus0 Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the timer in SMB0CR. When SCL goes high, the timer in SMB0CR counts up. A timer overflow indicates a free bus timeout: if SMBus0 is waiting to generate a START, it will do so after this timeout. The bus free period should be less than 50 µs (see Figure 18.9, SMBus0 Clock Rate Register) ...
Page 191
... Bit1: FTE: SMBus Free Timer Enable Bit 0: No timeout when SCL is high 1: Timeout when SCL high time exceeds limit specified by the SMB0CR value. Bit0: TOE: SMBus Timeout Enable Bit 0: No timeout when SCL is low. C8051F020/1/2/3 R/W R/W R/W R/W STO SI AA ...
Page 192
... C8051F020/1/2/3 18.4.2. Clock Rate Register Figure 18.9. SMB0CR: SMBus0 Clock Rate Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SMB0CR.[7:0]: SMBus0 Clock Rate Preset The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The timer counts up, and when it rolls over to 0x00, the SCL logic state toggles ...
Page 193
... SLV6 is the most significant bit of the address and corresponds to the first bit of the address byte received. Bit0: GC: General Call Address Enable. This bit is used to enable general call address (0x00) recognition. 0: General call address is ignored. 1: General call address is recognized. C8051F020/1/2/3 R/W R/W R/W R/W Bit4 Bit3 ...
Page 194
... C8051F020/1/2/3 18.4.5. Status Register The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 interface. There are 28 possible SMBus0 states, each with a corresponding unique status code. The five most significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at zero when SI = ‘1’. Therefore, all possible status codes are multiples of eight ...
Page 195
... Slave Address + R transmitted. NACK received. 0x50 Data byte received. ACK transmitted. 0x58 Data byte received. NACK transmitted. C8051F020/1/2/3 Typical Action Load SMB0DAT with Slave Address + R/W. Clear STA. Load SMB0DAT with Slave Address + R/W. Clear STA. Load SMB0DAT with data to be transmit- ted ...
Page 196
... C8051F020/1/2/3 Table 18.1. SMB0STA Status Codes and States Status Mode Code 0x60 Own slave address + W received. ACK trans- mitted. 0x68 Arbitration lost in sending SLA + R/W as mas- ter. Own address + W received. ACK transmit- ted. 0x70 General call address received. ACK transmit- ted. ...
Page 197
... SPI0DAT SFR Bus SFR Bus SPI0CFG SPI0CN Bit Count Logic SPI CONTROL LOGIC SPI Clock Pin Control (Master Mode) Interface SCK MOSI Tx Data Pin SPI0DAT Control Logic Shift Register MISO Rx Data NSS Read SPI0DAT Rev. 1.4 C8051F020/1/2/3 I SPI IRQ Port I 197 ...
Page 198
... C8051F020/1/2/3 19.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 19.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master, and an input when SPI0 is operating as a slave ...
Page 199
... The new data is not transferred to the receive buf- fer, allowing the previously received data byte to be read. The data byte causing the overrun is lost. MOSI MOSI MISO MISO VDD NSS NSS SCK SCK Px.y Rev. 1.4 C8051F020/1/2/3 SLAVE DEVICE SPI SHIFT REGISTER Receive Buffer 199 ...
Page 200
... C8051F020/1/2/3 Multiple masters may reside on the same bus. A Mode Fault flag (MODF, SPI0CN.5) is set to logic 1 when SPI0 is configured as a master (MSTEN = 1) and its slave select signal NSS is pulled low. When the Mode Fault flag is set, the MSTEN and SPIEN bits of the SPI control register are cleared by hardware, thereby placing the SPI0 module in an " ...