C8051F021 Silicon Laboratories Inc, C8051F021 Datasheet - Page 178

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C8051F021

Manufacturer Part Number
C8051F021
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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C8051F020/1/2/3
Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to assume a high-
impedance state. The Open-Drain configuration is useful to prevent contention between devices in systems where the
Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire.
The output modes of the Port pins on Ports 4 through 7 are determined by the bits in the P74OUT register (see
Figure 17.20). Each bit in P74OUT controls the output mode of a 4-bit bank of Port pins on Ports 4, 5, 6, and 7. A
logic 1 in P74OUT.7 will configure the output modes of 4 most-significant bits of Port 7, P7.[7:4], to Push-Pull; a
logic 0 in P74OUT.7 will configure the output modes of P7.[7:4] to Open-Drain.
17.2.3. Configuring Port Pins as Digital Inputs
A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the
associated bit in the Port Data register. For example, P7.7 is configured as a digital input by setting P74OUT.7 to a
logic 0 and P7.7 to a logic 1.
17.2.4. Weak Pull-ups
By default, each Port pin has an internal weak pull-up device enabled which provides a resistive connection (about
100 k) between the pin and VDD. The weak pull-up devices can be globally disabled by writing a logic 1 to the
Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically deactivated on any pin that is
driving a logic 0; that is, an output pin will not contend with its own pull-up device.
17.2.5. External Memory Interface
If the External Memory Interface (EMIF) is enabled on the High ports (Ports 4 through 7), EMIFLE (XBR2.1) should
be set to a logic 0.
If the External Memory Interface is enabled on the High ports and an off-chip MOVX operation occurs, the External
Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX
instruction, regardless of the settings of the Port Data registers. The output configuration of the Port pins is not
affected by the EMIF operation, except that Read operations will explicitly disable the output drivers on the Data Bus
during the MOVX execution. See
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP
XRAM” on page 145
for more information about the External Memory Interface.
178
Rev. 1.4

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