C8051F310 Silicon Laboratories Inc, C8051F310 Datasheet
C8051F310
Specifications of C8051F310
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C8051F310 Summary of contents
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... MIPS throughput with 25 MHz clock - Expanded interrupt handler DD Memory - 1280 bytes internal data RAM (1024 + 256 (C8051F310/1/6/ (C8051F312/3/4/5) Flash; In-system programmable in 512-byte sectors Digital Peripherals 29/25/21 Port I/O; - All 5 V tolerant with high sink current - Hardware enhanced UART, SMBus™, and SPI™ ...
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... C8051F310/1/2/3/4/5/6 OTES 2 Rev. 1.7 ...
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... Analog to Digital Converter..................................................................... 33 1.8. Comparators ..................................................................................................... 34 2. Absolute Maximum Ratings .................................................................................. 35 3. Global DC Electrical Characteristics .................................................................... 36 4. Pinout and Package Definitions............................................................................ 39 5. 10-Bit ADC (ADC0, C8051F310/1/2/3/6 only) ........................................................ 51 5.1. Analog Multiplexer ............................................................................................ 51 5.2. Temperature Sensor ......................................................................................... 52 5.3. Modes of Operation .......................................................................................... 54 5.3.1. Starting a Conversion............................................................................... 54 5.3.2. Tracking Modes........................................................................................ 55 5 ...
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... C8051F310/1/2/3/4/5/6/7 8.3.4. Interrupt Latency ...................................................................................... 95 8.3.5. Interrupt Register Descriptions................................................................. 97 8.4. Power Management Modes ............................................................................ 102 8.4.1. Idle Mode................................................................................................ 102 8.4.2. Stop Mode .............................................................................................. 103 9. Reset Sources....................................................................................................... 105 9.1. Power-On Reset ............................................................................................. 106 9.2. Power-Fail Reset / V DD 9.3. External Reset ................................................................................................ 107 9.4. Missing Clock Detector Reset......................................................................... 108 9 ...
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... Timer with Auto-Reload................................................................ 195 17.2.2.8-bit Timers with Auto-Reload................................................................ 196 17.3.Timer 3 .......................................................................................................... 199 17.3.1.16-bit Timer with Auto-Reload................................................................ 199 17.3.2.8-bit Timers with Auto-Reload................................................................ 200 18. Programmable Counter Array ............................................................................ 203 18.1.PCA Counter/Timer ........................................................................................ 204 18.2.Capture/Compare Modules ............................................................................ 205 18.2.1.Edge-triggered Capture Mode................................................................ 206 18.2.2.Software Timer (Compare) Mode........................................................... 207 C8051F310/1/2/3/4/5/6/7 Rev. 1.7 5 ...
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... C8051F310/1/2/3/4/5/6/7 18.2.3.High-Speed Output Mode ...................................................................... 208 18.2.4.Frequency Output Mode ........................................................................ 209 18.2.5.8-Bit Pulse Width Modulator Mode......................................................... 210 18.2.6.16-Bit Pulse Width Modulator Mode....................................................... 211 18.3.Watchdog Timer Mode ................................................................................... 212 18.3.1.Watchdog Timer Operation .................................................................... 212 18.3.2.Watchdog Timer Usage ......................................................................... 213 18.4.Register Descriptions for PCA........................................................................ 215 19. Revision Specific Behavior ................................................................................. 221 19 ...
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... List of Figures 1. System Overview Figure 1.1. C8051F310 Block Diagram .................................................................... 19 Figure 1.2. C8051F311 Block Diagram .................................................................... 20 Figure 1.3. C8051F312 Block Diagram .................................................................... 21 Figure 1.4. C8051F313 Block Diagram .................................................................... 22 Figure 1.5. C8051F314 Block Diagram .................................................................... 23 Figure 1.6. C8051F315 Block Diagram .................................................................... 24 Figure 1.7. C8051F316 Block Diagram .................................................................... 25 Figure 1.8. C8051F317 Block Diagram .................................................................... 26 Figure 1 ...
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... C8051F310/1/2/3/4/5/6/7 7. Comparators Figure 7.1. Comparator0 Functional Block Diagram ................................................ 69 Figure 7.2. Comparator1 Functional Block Diagram ................................................ 70 Figure 7.3. Comparator Hysteresis Plot ................................................................... 71 8. CIP-51 Microcontroller Figure 8.1. CIP-51 Block Diagram............................................................................ 79 Figure 8.2. Memory Map .......................................................................................... 85 9. Reset Sources Figure 9.1. Reset Sources...................................................................................... 105 Figure 9.2. Power-On and V 10 ...
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... Figure 18.8. PCA 8-Bit PWM Mode Diagram ......................................................... 210 Figure 18.9. PCA 16-Bit PWM Mode...................................................................... 211 Figure 18.10. PCA Module 4 with Watchdog Timer Enabled ................................. 212 19. Revision Specific Behavior Figure 19.1. Reading Package Marking ................................................................. 221 20. C2 Interface Figure 20.1. Typical C2 Pin Sharing....................................................................... 225 C8051F310/1/2/3/4/5/6/7 Rev. 1.7 9 ...
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... C8051F310/1/2/3/4/5/6 OTES 10 Rev. 1.7 ...
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... Table 4.1. Pin Definitions for the C8051F31x .......................................................... 39 Table 4.2. LQFP-32 Package Dimensions .............................................................. 42 Table 4.3. QFN-28 Package Dimensions ................................................................ 44 Table 4.4. QFN-24 Package Dimensions ................................................................ 48 5. 10-Bit ADC (ADC0, C8051F310/1/2/3/6 only) Table 5.1. ADC0 Electrical Characteristics .............................................................. 65 6. Voltage Reference (C8051F310/1/2/3/6 only) Table 6.1. External Voltage Reference Circuit Electrical Characteristics ................ 68 7 ...
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... C8051F310/1/2/3/4/5/6/7 15. UART0 Table 15.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator ............................................................... 170 Table 15.2. Timer Settings for Standard Baud Rates Using an External 25 MHz Oscillator .................................................. 170 Table 15.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 171 Table 15.4. Timer Settings for Standard Baud Rates ...
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... SFR Definition 12.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 13.1. XBR0: Port I/O Crossbar Register 134 SFR Definition 13.2. XBR1: Port I/O Crossbar Register 135 SFR Definition 13.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 SFR Definition 13.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 C8051F310/1/2/3/4/5/6/7 Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . . 107 DD Rev. 1.7 13 ...
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... C8051F310/1/2/3/4/5/6/7 SFR Definition 13.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 137 SFR Definition 13.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SFR Definition 13.7. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SFR Definition 13.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SFR Definition 13.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 139 SFR Definition 13.10. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SFR Definition 13 ...
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... SFR Definition 18.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 219 C2 Register Definition 20.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 C2 Register Definition 20.2. DEVICEID: C2 Device 223 C2 Register Definition 20.3. REVID: C2 Revision 224 C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 224 C2 Register Definition 20.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 224 C8051F310/1/2/3/4/5/6/7 Rev. 1.7 15 ...
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... C8051F310/1/2/3/4/5/6 OTES 16 Rev. 1.7 ...
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... True 10-bit 200 ksps 25-channel single-ended/differential ADC with analog multiplexer (C8051F310/1/2/3/6) • Precision programmable 25 MHz internal oscillator • (C8051F310/1/6/ (C8051F312/3/4/5) of on-chip Flash memory • 1280 bytes of on-chip RAM • SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware • ...
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... C8051F310/1/2/3/4/5/6/7 Table 1.1. Product Selection Guide C8051F310 25 16 1280 C8051F310- 1280 C8051F311 25 16 1280 C8051F311- 1280 C8051F312 25 8 1280 C8051F312- 1280 C8051F313 25 8 1280 C8051F313- 1280 C8051F314 25 8 1280 C8051F314- 1280 C8051F315 25 8 1280 C8051F315- 1280 C8051F316- 1280 C8051F317- 1280 18 ...
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... Analog/Digital Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.1. C8051F310 Block Diagram C8051F310/1/2/3/4/5/6/7 Port 0 Latch Port 1 Latch UART 8 16kbyte Timer FLASH 0 0,1,2,3 / RTC 5 256 byte SRAM PCA/ 1 WDT ...
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... C8051F310/1/2/3/4/5/6/7 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.2. C8051F311 Block Diagram 20 Port 0 Latch Port 1 Latch UART 8 16kbyte Timer FLASH 0 0,1,2,3 / RTC 5 Reset 256 byte SRAM PCA/ 1 WDT ...
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... Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.3. C8051F312 Block Diagram C8051F310/1/2/3/4/5/6/7 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 256 byte SRAM PCA/ 1 WDT 1K byte SRAM ...
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... C8051F310/1/2/3/4/5/6/7 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.4. C8051F313 Block Diagram 22 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 Reset 256 byte SRAM PCA/ 1 WDT 1K byte ...
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... Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.5. C8051F314 Block Diagram C8051F310/1/2/3/4/5/6/7 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 256 byte SRAM PCA/ 1 WDT 1K byte SRAM ...
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... C8051F310/1/2/3/4/5/6/7 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.6. C8051F315 Block Diagram 24 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 Reset 256 byte SRAM PCA/ 1 WDT 1K byte ...
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... Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.7. C8051F316 Block Diagram C8051F310/1/2/3/4/5/6/7 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 256 byte SRAM PCA/ 1 WDT 1 kB SRAM ...
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... C8051F310/1/2/3/4/5/6/7 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.8. C8051F317 Block Diagram 26 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 Reset 256 byte SRAM PCA/ 1 WDT 1 kB ...
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... With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.9 shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum sys- tem clocks Silicon Labs (25 MHz clk) Figure 1.9. Comparison of Peak MCU Execution Speeds C8051F310/1/2/3/4/5/6/7 2 2 Microchip Philips ...
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... C8051F310/1/2/3/4/5/6/7 1.1.3. Additional Features The C8051F31x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as opposed to 7 for the stan- dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...
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... Byte Sectors) 0x0000 C8051F312/3/4/5 RESERVED 0x2000 0x1FFF 8 kB Flash (In-System Programmable in 512 Byte Sectors) 0x0000 Figure 1.11. On-Board Memory Map C8051F310/1/2/3/4/5/6/7 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE 0xFF Upper 128 RAM (Indirect Addressing Only) 0x80 0x7F (Direct and Indirect Addressing) 0x30 ...
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... All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them synchronized. The C8051F310DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F31x MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, a debug adapter, a target application board with the associated MCU installed, and the required cables and wall-mount power supply ...
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... Programmable Digital I/O and Crossbar C8051F310/2/4 devices include 29 I/O pins (three byte-wide Ports and one 5-bit-wide Port); C8051F311/3/5 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F316/7 devices include 21 I/O pins (one byte-wide Port, two 6-bit-wide Ports and one 1-bit-wide Port). The C8051F31x Ports behave like typical 8051 Ports with a few enhancements ...
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... C8051F310/1/2/3/4/5/6/7 1.5. Serial Ports The C8051F31x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. ...
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... Analog to Digital Converter The C8051F310/1/2/3/6 devices include an on-chip 10-bit SAR ADC with a 25-channel differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit accuracy with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and nega- tive ADC inputs. Ports1-3 are available as an ADC inputs ...
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... C8051F310/1/2/3/4/5/6/7 1.8. Comparators C8051F31x devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. ...
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... This is a stress rating only and functional operation of the devices at those or any other condi- tions above those indicated in the operation listings of this specification is not implied. Exposure to maxi- mum rating conditions for extended periods may affect device reliability. C8051F310/1/2/3/4/5/6/7 Conditions Min – ...
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... C8051F310/1/2/3/4/5/6/7 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40°C to +85°C, 25 MHz System Clock unless otherwise specified. Parameter Digital Supply Voltage Digital Supply RAM Data Retention Voltage Specified Operating Temperature Range SYSCLK (system clock frequency) Tsysl (SYSCLK low time) Tsysh (SYSCLK high time) Digital Supply Current— ...
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... MHz by multiplying the frequency of interest by the DD frequency sensitivity number for that range. When using these numbers to estimate Idle I MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: 3 MHz, Idle C8051F310/1/2/3/4/5/6/7 Conditions MHz 3 MHz ...
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... C8051F310/1/2/3/4/5/6/7 Other electrical characteristics tables are found in the data sheet section corresponding to the associated peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page indicated in Table 3.2. Table 3.2. Electrical Characteristics Quick Reference Peripheral Electrical Characteristics ADC0 Electrical Characteristics ...
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... C8051F310/1/2/3/4/5/6/7 Type Description Power Supply Voltage Ground. D I/O Device Reset. Open-drain output of internal POR. An external source can initiate a system reset by driving 5 this pin low for at least 10 µs. D I/O Clock signal for the C2 Debug Interface. D I/O Port 3.0. See ...
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... C8051F310/1/2/3/4/5/6/7 Table 4.1. Pin Definitions for the C8051F31x (Continued) Pin Numbers Name ‘F310/2/4 ‘F311/3/5 ‘F316 P3.1 7 P3.2 8 P3 Type Description D I Port 1.5. See Section I/O or Port 1.6. See Section I/O or Port 1.7. See Section 13 ...
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... P0 P0.0 3 GND VDD 4 5 /RST/C2CK P3.0/C2D 6 P3 P3.2 Figure 4.1. LQFP-32 Pinout Diagram (Top View) C8051F310/1/2/3/4/5/6/7 C8051F310/2/4 Top View Rev. 1.7 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 P1.7 18 P2.0 17 P2.1 41 ...
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... C8051F310/1/2/3/4/5/6 PIN 1 IDENTIFIER Figure 4.2. LQFP-32 Package Diagram 42 Table 4.2. LQFP-32 Package Dimensions MIN 0.05 A2 1. Rev. 1.7 MM TYP MAX - 1.60 - 0.15 1.40 1.45 0.37 0.45 9.00 - 7.00 - 0.80 - 9.00 - 7.00 - 0.60 0.75 ...
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... GND P0.1 1 P0.0 2 GND 3 C8051F311/3/5 VDD 4 /RST/C2CK 5 P3.0/C2D 6 P2.7 7 Figure 4.3. QFN-28 Pinout Diagram (Top View) C8051F310/1/2/3/4/5/6/7 Top View GND Rev. 1.7 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 P1.6 15 P1.7 43 ...
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... C8051F310/1/2/3/4/5/6/7 Bottom View DETAIL Side View DETAIL 1 Figure 4.4. QFN-28 Package Drawing Rev. 1.7 Table 4.3. QFN-28 Package Dimensions MM MIN TYP MAX A 0.80 0.90 1. 0.02 0. 0. 0.18 0. 2.90 3. 2.90 3. 0.45 0. 0.435 - BB - 0.435 ...
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... Optional GND Connection L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.5. Typical QFN-28 Landing Diagram C8051F310/1/2/3/4/5/6/7 Top View E2 E Rev. 1.7 0. ...
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... C8051F310/1/2/3/4/5/6/7 0.50 mm 0.60 mm 0. 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.6. QFN-28 Solder Paste Recommendation 46 Top View 0.60 mm 0.30 mm 0. Rev. 1.7 0.85 mm ...
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... P0.1 1 P0.0 2 GND 3 VDD 4 /RST / C2CK 5 P3.0 / C2D 6 Figure 4.7. QFN-24 Pinout Diagram (Top View) C8051F310/1/2/3/4/5/6/7 C8051F316/7 Top View GND Rev. 1.7 18 P1.0 17 P1.1 16 P1.2 15 P1.3 14 P1.4 13 P1.5 47 ...
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... C8051F310/1/2/3/4/5/6/7 Bottom View Side View e Figure 4.8. QFN-24 Package Drawing 48 Table 4.4. QFN-24 Package Dimensions Rev. 1.7 MM MIN TYP MAX 0.70 0.75 0.80 0.00 0.02 0.05 — 0.50 — — 0.25 — 0.18 0.25 0.30 — 4.00 — 2.50 2.60 2.70 — ...
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... Pin #1 Optional GND Connection 0.20 mm 0.30 mm 0.35 mm 0.45 mm 0.75 mm 0.10 mm Figure 4.9. Typical QFN-24 Landing Diagram C8051F310/1/2/3/4/5/6/7 Top View E2 E Rev. 1.7 49 ...
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... C8051F310/1/2/3/4/5/6/7 Pin #1 0.80 mm 0.20 mm 0.30 mm 0.35 mm 0.45 mm 0.75 mm 0.10 mm Figure 4.10. QFN-24 Solder Paste Recommendation 50 Top View 0.60 mm 0.45 mm 0.30 mm 0.20 mm 0. Rev. 1.7 ...
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... ADC (ADC0, C8051F310/1/2/3/6 only) The ADC0 subsystem for the C8051F310/1/2/3/6 consists of two analog multiplexers (referred to collec- tively as AMUX0) with 25 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to measure P1.0– ...
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... C8051F310/1/2/3/4/5/6/7 Inputs are measured from ‘0’ to VREF * 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’. Input Voltage Right-Justified ADC0H:ADC0L VREF x 1023/1024 VREF x 512/1024 VREF x 256/1024 0 When in Differential Mode, conversion codes are represented as 10-bit signed 2’ ...
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... Figure 5.3. Temperature Sensor Error with 1-Point Calibration C8051F310/1/2/3/4/5/6/7 40.00 0.00 20.00 Temperature (degrees C) Rev. 1.7 5.00 4.00 3.00 2.00 1.00 0.00 60.00 80.00 -1.00 -2 ...
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... C8051F310/1/2/3/4/5/6/7 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 AD0SC 31). 5.3.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2-0) in register ADC0CN ...
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... Timer 0, Timer 2, Timer 1, Timer 3 Overflow (AD0CM[2:0]=000, 001,010 011, 101) SAR Clocks Low Power AD0TM=1 or Convert SAR Clocks Track or AD0TM=0 Convert Figure 5.4. 10-Bit ADC Track and Conversion Example Timing C8051F310/1/2/3/4/5/6/7 56 Track Convert Track or Convert Convert B. ADC0 Timing for Internal Trigger Source 1 ...
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... C8051F310/1/2/3/4/5/6/7 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accu- racy required for the conversion ...
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... Notes: 1. Only applies to C8051F310/1/2/3/4/5; selection RESERVED on C8051F316/7 devices. 2. Only applies to C8051F310/2; selection RESERVED on C8051F311/3/6/7 devices. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 Bit2 ADC0 Positive Input P1.0 P1.1 P1 ...
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... Notes: 1. Only applies to C8051F310/1/2/3/4/5; selection RESERVED on C8051F316/7 devices. 2. Only applies to C8051F310/2; selection RESERVED on C8051F311/3/6/7 devices. 58 R/W R/W R/W AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000 Bit4 Bit3 Bit2 ADC0 Negative Input P1.0 P1.1 P1.2 P1 ...
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... Bits7–0: ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always read ‘0’. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W ...
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... C8051F310/1/2/3/4/5/6/7 SFR Definition 5.6. ADC0CN: ADC0 Control R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. ...
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... Bits7–0: High byte of ADC0 Greater-Than Data Word. SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Greater-Than Data Word. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W ...
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... C8051F310/1/2/3/4/5/6/7 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Less-Than Data Word. ...
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... ADC0LTH:ADC0LTL 0x1FC0 0x1040 VREF x (64/1024) 0x1000 ADC0GTH:ADC0GTL 0x0FC0 AD0WINT not affected 0x0000 0 Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data C8051F310/1/2/3/4/5/6/7 ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF 0x0081 VREF x (128/1024) 0x0080 0x007F AD0WINT=1 0x0041 VREF x (64/1024) 0x0040 ...
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... C8051F310/1/2/3/4/5/6/7 5.4.2. Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are rep- resented as 10-bit 2’ ...
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... Linearity* Gain* Offset* Power Specifications Power Supply Current (V supplied to ADC0) DD Power Supply Rejection *Note: Represents one standard deviation from the mean. Includes ADC offset, gain, and linearity variations. C8051F310/1/2/3/4/5/6/7 Conditions Min — Guaranteed Monotonic — –12 Differential mode –15 — ...
Page 66
... C8051F310/1/2/3/4/5/6 OTES 66 Rev. 1.7 ...
Page 67
... Voltage Reference (C8051F310/1/2/3/6 only) The voltage reference MUX on C8051F310/1/2/3/6 devices is configurable to use an externally connected voltage reference, or the power supply voltage (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For an external source, REFSL should be set to ‘0’; For V as the reference source, REFSL should be set to ‘ ...
Page 68
... C8051F310/1/2/3/4/5/6/7 SFR Definition 6.1. REF0CN: Reference Control R/W R/W R/W Bit7 Bit6 Bit5 Bits7–4: UNUSED. Read = 0000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF input pin used as voltage reference. ...
Page 69
... CMX0N1 CP0HYP0 CMX0N0 CP0HYN1 CP0HYN0 CMX0P1 CMX0P0 P1.0 P1.4 P2.0 P2.4 P1.1 P1.5 P2.1 P2.5 Figure 7.1. Comparator0 Functional Block Diagram C8051F310/1/2/3/4/5/6/7 133). Comparator0 may also be used as a 108). Section “13.3. General Purpose Port I/O” on page VDD CP0 + + SET SET ...
Page 70
... C8051F310/1/2/3/4/5/6/7 The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis- abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to less than 100 nA ...
Page 71
... Therefore recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. This Power Up Time is specified in Table 7.1 on page 78. C8051F310/1/2/3/4/5/6/7 + CP0 ...
Page 72
... C8051F310/1/2/3/4/5/6/7 SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. Bit5: CP0RIF: Comparator0 Rising-Edge Interrupt Flag. ...
Page 73
... Bits3–2: UNUSED. Read = 00b, Write = don’t care. Bits1–0: CMX0P1–CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P1 CMX0P0 Positive Input C8051F310/1/2/3/4/5/6/7 R/W R/W R/W R CMX0P1 CMX0P0 00000000 Bit4 Bit3 Bit2 Bit1 P1.1 P1 ...
Page 74
... C8051F310/1/2/3/4/5/6/7 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled. 1: Comparator rising-edge interrupt enabled. Bit4: CP0FIE: Comparator Falling-Edge Interrupt Enable. ...
Page 75
... Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit4 Bit3 Bit2 Rev ...
Page 76
... C8051F310/1/2/3/4/5/6/7 SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection R/W R/W R CMX1N1 CMX1N0 Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bits5–4: CMX1N1–CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input. ...
Page 77
... Comparator falling-edge interrupt disabled. 1: Comparator falling-edge interrupt enabled. Bits1–0: CP1MD1–CP1MD0: Comparator1 Mode Select. These bits select the response time for Comparator1. Mode CP1MD1 CP1MD0 C8051F310/1/2/3/4/5/6/7 R/W R/W R/W CP1FIE - - CP1MD1 CP1MD0 00000010 Bit4 Bit3 Bit2 CP1 Response Time (TYP) 0 Fastest Response Time 1 — ...
Page 78
... C8051F310/1/2/3/4/5/6/7 Table 7.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter Response Time: 1 Mode 0, Vcm = 1.5 V Response Time: 1 Mode 1, Vcm = 1.5 V Response Time: 1 Mode 2, Vcm = 1.5 V Response Time: ...
Page 79
... PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE Figure 8.1. CIP-51 Block Diagram C8051F310/1/2/3/4/5/6/7 Section 17), an enhanced full-duplex UART (see description Section 16), 256 bytes of internal RAM, 128 byte (Section 8.2.6), and 29 Port I/O (see description Port I/O - Extended Interrupt Handler ...
Page 80
... C8051F310/1/2/3/4/5/6/7 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...
Page 81
... AND indirect RAM to A ANL A, #data AND immediate to A ANL direct, A AND A to direct byte ANL direct, #data AND immediate to direct byte ORL Register to A C8051F310/1/2/3/4/5/6/7 Section “10. Flash Memory” on page 111 Arithmetic Operations Logical Operations Rev. 1.7 for Clock Bytes Cycles ...
Page 82
... C8051F310/1/2/3/4/5/6/7 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ORL A, direct OR direct byte to A ORL A, @Ri OR indirect RAM to A ORL A, #data OR immediate to A ORL direct direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct ...
Page 83
... Compare immediate to indirect and jump if not CJNE @Ri, #data, rel equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation C8051F310/1/2/3/4/5/6/7 Boolean Manipulation Program Branching Rev. 1.7 Clock Bytes Cycles ...
Page 84
... C8051F310/1/2/3/4/5/6/7 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. ...
Page 85
... Byte Sectors) 0x0000 8.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F310/1 and C8051F312/3/4/5 imple- ment 16 and 8 kB, respectively, of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF or 0x0000 to 0x1FFF. ...
Page 86
... C8051F310/1/2/3/4/5/6/7 8.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca- tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...
Page 87
... SBUF0 CPT1CN 90 P1 TMR3CN TMR3RLL 88 TCON TMOD TL0 DPL 0(8) 1(9) 2(A) (bit addressable) C8051F310/1/2/3/4/5/6/7 PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN P2MDIN P3MDIN IT01CF PCA0CPM3 PCA0CPM4 P0SKIP P1SKIP TMR2RLH TMR2L TMR2H ADC0GTL ADC0GTH ADC0LTL AMX0P ADC0CF ADC0L OSCICL SPI0DAT P0MDOUT P1MDOUT P2MDOUT P3MDOUT ...
Page 88
... C8051F310/1/2/3/4/5/6/7 Table 8.3. Special Function Registers Register Address Description SFRs are listed in alphabetical order. All undefined SFR locations are reserved ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ...
Page 89
... Timer/Counter 1 High TL0 0x8A Timer/Counter 0 Low TL1 0x8B Timer/Counter 1 Low TMOD 0x89 Timer/Counter Mode TMR2CN 0xC8 Timer/Counter 2 Control TMR2H 0xCD Timer/Counter 2 High C8051F310/1/2/3/4/5/6/7 Rev. 1.7 Page 141 142 142 143 215 219 219 219 219 219 218 218 218 218 ...
Page 90
... C8051F310/1/2/3/4/5/6/7 Table 8.3. Special Function Registers (Continued) Register Address Description TMR2L 0xCC Timer/Counter 2 Low TMR2RLH 0xCB Timer/Counter 2 Reload High TMR2RLL 0xCA Timer/Counter 2 Reload Low TMR3CN 0x91 Timer/Counter 3Control TMR3H 0x95 Timer/Counter 3 High TMR3L 0x94 Timer/Counter 3Low TMR3RLH 0x93 Timer/Counter 3 Reload High ...
Page 91
... R/W R/W Bit7 Bit6 Bit5 Bits7–0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 ...
Page 92
... C8051F310/1/2/3/4/5/6/7 SFR Definition 8.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared to logic 0 by all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition borrow from (subtraction) the high order nibble ...
Page 93
... Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI) C8051F310/1/2/3/4/5/6 Register R/W ...
Page 94
... C8051F310/1/2/3/4/5/6/7 instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 8.3.1. MCU Interrupt Sources and Vectors The MCUs support 14 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend- ing flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag ...
Page 95
... DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. C8051F310/1/2/3/4/5/6/7 (Section “17.1. Timer 0 and Timer 1” on page IT1 ...
Page 96
... C8051F310/1/2/3/4/5/6/7 Table 8.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B RESERVED 0x0043 ADC0 Window Compare 0x004B ADC0 Conversion ...
Page 97
... Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. Bit0: EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W R/W ES0 ET1 ...
Page 98
... C8051F310/1/2/3/4/5/6/7 SFR Definition 8.8. IP: Interrupt Priority R/W R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. ...
Page 99
... Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). Bit1: RESERVED. Read = 0. Must Write 0. Bit0: ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W EPCA0 EADC0 EWADC0 Reserved Bit4 ...
Page 100
... C8051F310/1/2/3/4/5/6/7 SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 PCP1 PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. ...
Page 101
... Port pin to a peripheral configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). IN0SL2–0 /INT0 Port Pin 000 001 010 011 100 101 110 111 C8051F310/1/2/3/4/5/6/7 R/W R/W R/W IN1SL0 IN0PL IN0SL2 IN0SL1 Bit4 Bit3 Bit2 P0.0 P0 ...
Page 102
... C8051F310/1/2/3/4/5/6/7 8.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states ...
Page 103
... Setting this bit will place the CIP-51 in Idle mode. This bit will always be read CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) C8051F310/1/2/3/4/5/6/7 PCON: Power Control R/W R/W ...
Page 104
... C8051F310/1/2/3/4/5/6 OTES 104 Rev. 1.7 ...
Page 105
... Px.x C0RSEF Missing Clock Detector (one- shot) EN System Clock CIP-51 Microcontroller Core Extended Interrupt Handler C8051F310/1/2/3/4/5/6/7 for information on selecting and configuring details the use of the Watchdog Timer). VDD Power On Reset Supply Monitor + '0' - Enable PCA WDT (Software Reset) SWRSF EN System Reset Figure 9 ...
Page 106
... C8051F310/1/2/3/4/5/6/7 9.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until additional delay occurs before the device is released from reset; the delay decreases as the V RST ramp time increases (V ramp time is defined as how fast V ...
Page 107
... RST pin generates a reset; an external pullup and/or decoupling of the RST pin may be necessary to avoid erroneous noise-induced resets. See Table 9.1 for complete RST pin spec- ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. C8051F310/1/2/3/4/5/6/7 monitor is enabled and a software reset is performed, the DD monitor ...
Page 108
... A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a MOVX write operation targets an address above address 0x3DFF for C8051F310/1 or 0x1FFF for C8051F312/3/4/5. • A Flash read is attempted above user code space. This occurs when a MOVC operation targets an address above address 0x3DFF for C8051F310/1 or 0x1FFF for C8051F312/3/4/5. • ...
Page 109
... Source of last reset was RST pin. Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read-modify-write instructions read and modify the source enable only. This applies to bits: C0RSEF, SWRSF, MCDRSF, PORSF. C8051F310/1/2/3/4/5/6/7 R/W R R/W SWRSF ...
Page 110
... C8051F310/1/2/3/4/5/6/7 Table 9.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I RST Output Low Voltage OL RST Input High Voltage RST Input Low Voltage RST = 0.0 V RST Input Pullup Current V Monitor Threshold ( RST Time from last system clock rising Missing Clock Detector Timeout ...
Page 111
... Step 3. Set the PSWE bit (register PSCTL). Step 4. Write the first key code to FLKEY: 0xA5. Step 5. Write the second key code to FLKEY: 0xF1. Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. C8051F310/1/2/3/4/5/6/7 Section “20. C2 Interface” Rev. 1.7 Monitor DD ...
Page 112
... MHz System Clock Write Cycle Time 25 MHz System Clock *Note: 512 bytes at locations 0x3E00 (C8051F310/1) are reserved. 10.2. Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX write instruction and read using the MOVC instruction ...
Page 113
... Unlocked FLASH Pages Access limit set according to the FLASH security lock byte Figure 10.1. Flash Program Memory Map C8051F310/1/2/3/4/5/6/7 11111101b 00000010b 3 (First two Flash pages + Lock Byte Page) 0x0000 to 0x03FF (first two Flash pages) and 0x3C00 to 0x3DFF or 0x1E00 to 0x1FFF (Lock Byte Page) ...
Page 114
... C8051F310/1/2/3/4/5/6/7 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Table 10.2 summarizes the Flash security features of the C8051F31x devices ...
Page 115
... Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser- viced in priority order after the Flash operation has been completed and interrupts have been re-enabled by software. C8051F310/1/2/3/4/5/6/7 Monitor DD rise time specification met. If the system cannot ...
Page 116
... C8051F310/1/2/3/4/5/6/7 10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your compiler documentation for instructions regarding how to explicitly locate variables in dif- ferent memory areas. 11. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine called with an illegal address does not result in modification of the Flash ...
Page 117
... Flash reads. At system clock frequen- cies below 10 MHz, disabling the Flash one-shot will increase system power consumption. 0: Flash one-shot disabled. 1: Flash one-shot enabled. Bits6–0: RESERVED. Read = 0. Must Write 0. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W R/W ...
Page 118
... C8051F310/1/2/3/4/5/6 OTES 118 Rev. 1.7 ...
Page 119
... MOVX command, effectively selecting a 256-byte page of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL determines which page of XRAM is accessed. For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed. C8051F310/1/2/3/4/5/6/7 Section “10. Flash Memory” on page 111 R/W R/W ...
Page 120
... C8051F310/1/2/3/4/5/6 OTES 120 Rev. 1.7 ...
Page 121
... Electrical specifications for the precision internal oscillator are given in Table 12.1 on page 123. Note that the system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset. C8051F310/1/2/3/4/5/6/7 OSCICL OSCICN ...
Page 122
... C8051F310/1/2/3/4/5/6/7 SFR Definition 12.1. OSCICL: Internal Oscillator Calibration R/W R/W R/W Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6–0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. This reset value for OSCICL deter- mines the oscillator base frequency ...
Page 123
... SYSCLK derived from the External Oscillator circuit. Table 12.1. Internal Oscillator Electrical Characteristics V = 2.7 to 3.6 V; –40 to +85 °C unless otherwise specified. DD Parameter Internal Oscillator Frequency Internal Oscillator Supply Current (from C8051F310/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Conditions Min 24 OSCICN ...
Page 124
... C8051F310/1/2/3/4/5/6/7 12.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 12. M ...
Page 125
... R = Pullup resistor value in k C MODE (Circuit from Figure 12.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired where frequency of clock in MHz C = capacitor value the XTAL2 pin Power Supply on MCU in volts DD C8051F310/1/2/3/4/5/6/7 R/W R R/W R/W XFCN2 XFCN1 Bit4 Bit3 Bit2 Bit1 RC (XOSCMD = 10x) f ...
Page 126
... C8051F310/1/2/3/4/5/6/7 12.4. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 12.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 12.4. For example ...
Page 127
... Assume pF MHz 150 MHz If a frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 12 22 150 = 0.146 MHz, or 146 kHz Therefore, the XFCN value to use in this example is 011b. C8051F310/1/2/3/4/5/6/7 Rev. 1.7 = 3.0 V and DD 127 ...
Page 128
... C8051F310/1/2/3/4/5/6 OTES 128 Rev. 1.7 ...
Page 129
... Port Input/Output Digital and analog resources are available through 29 I/O pins (C8051F310/2/4 I/O pins (C8051F311/3/5 I/O pins (C8051F316/7). Port pins are organized as three byte-wide Ports and one 5-bit-wide (C8051F310/2/4) or 1-bit-wide (C8051F311/3/5) Port. In the C8051F316/7, the port pins are organized as one byte-wide Port, two 6-bit-wide Ports and one 1-bit-wide Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input ...
Page 130
... C8051F310/1/2/3/4/5/6/7 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT ANALOG INPUT PORT-INPUT Figure 13.2. Port I/O Cell Block Diagram 130 VDD GND Analog Select Rev. 1.7 VDD (WEAK) PORT PAD ...
Page 131
... Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. *Note: NSS is only pinned out in 4-wire SPI mode. Note: P1.6,P1.7,P2.6,P2.7 only available on the C8051F310/1/2/3/4/5; P1SKIP[7:6] should always be set to 11b for the C8051F316/7 devices. Figure 13.3. Crossbar Priority Decoder with No Pins Skipped ...
Page 132
... Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. *Note: NSS is only pinned out in 4-wire SPI mode. Note: P1.6,P1.7,P2.6,P2.7 only available on the C8051F310/1/2/3/4/5; P1SKIP[7:6] should always be set to 11b for the C8051F316/7 devices. Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins ...
Page 133
... Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. C8051F310/1/2/3/4/5/6/7 Rev. 1.7 133 ...
Page 134
... C8051F310/1/2/3/4/5/6/7 SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP1AE CP1E CP0AE Bit7 Bit6 Bit5 Bit7: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. Bit6: CP1E: Comparator1 Output Enable 0: CP1 unavailable at Port pin. ...
Page 135
... Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SET, when the destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written back to the SFR. C8051F310/1/2/3/4/5/6/7 R/W R/W ...
Page 136
... C8051F310/1/2/3/4/5/6/7 SFR Definition 13.3. P0: Port0 R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7–0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0). Read - Always reads ‘1’ if selected as analog input in register P0MDIN. Directly reads Port pin when configured as digital input ...
Page 137
... These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W R/W ...
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... C8051F310/1/2/3/4/5/6/7 SFR Definition 13.7. P1: Port1 R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘1’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input ...
Page 139
... Corresponding P1.n pin is skipped by the Crossbar. Note: Only P1.0–P1.5 are associated with Port pins on the C8051F316/7 devices. Hence, in C8051F316/7 devices, user code writing to this SFR should always set P1SKIP[7:6] = 11b so that those two pins are skipped by the crossbar decoder. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W Bit4 ...
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... C8051F310/1/2/3/4/5/6/7 SFR Definition 13.11. P2: Port2 R/W R/W R/W P2.7 P2.6 P2.5 Bit7 Bit6 Bit5 Bits7–0: P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0). Read - Always reads ‘1’ if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input ...
Page 141
... ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P2.n pin is not skipped by the Crossbar. 1: Corresponding P2.n pin is skipped by the Crossbar. Note: Only P2.0–P2.3 are associated with the Crossbar. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 ...
Page 142
... Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P3.n pin is configured as an analog input. 1: Corresponding P3.n pin is not configured as an analog input. Note: Only P3.0–P3.4 are associated with Port pins on C8051F310/2/4 devices; Only P3.0 is associated with a Port pin on C8051F311/3/5/6/7 devices. 142 R/W R/W ...
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... P3MDIN is logic 0. 0: Corresponding P3.n Output is open-drain. 1: Corresponding P3.n Output is push-pull. Note: Only P3.0–P3.4 are associated with Port pins on C8051F310/2/4 devices; Only P3.0 is associated with a Port pin on C8051F311/3/5/6/7 devices. Table 13.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified ...
Page 144
... C8051F310/1/2/3/4/5/6 OTES 144 Rev. 1.7 ...
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... SMBUS CONTROL LOGIC Arbitration Interrupt SCL Synchronization Request SCL Generation (Master Mode) SDA Control IRQ Generation Figure 14.1. SMBus Block Diagram C8051F310/1/2/3/4/5/6 Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL Control Data Path SDA Control Control SMB0DAT FILTER Rev. 1.7 SCL ...
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... C8051F310/1/2/3/4/5/6/7 14.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: • The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. • The I2C-Bus Specification—Version 2.0, Philips Semiconductor. • System Management Bus Specification—Version 1.1, SBS Implementers Forum. ...
Page 147
... LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The win- ning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. C8051F310/1/2/3/4/5/6/7 SLA5-0 R/W D7 ...
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... C8051F310/1/2/3/4/5/6/7 14.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency ...
Page 149
... Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in tion Register” on page 150. C8051F310/1/2/3/4/5/6/7 for more details on transmission 153; Table 14.4 provides a quick SMB0CN decoding refer- Section “14.4.1. SMBus Configura- Rev. 1.7 Section 149 ...
Page 150
... C8051F310/1/2/3/4/5/6/7 14.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins ...
Page 151
... SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 14.4). When a Free Timeout is detected, the interface will respond STOP was detected (an interrupt will be generated, and STO will be set). C8051F310/1/2/3/4/5/6/7 T SCL High Timeout High Minimum SDA Hold Time – ...
Page 152
... C8051F310/1/2/3/4/5/6/7 SFR Definition 14.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. ...
Page 153
... Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 14.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 14.4 for SMBus sta- tus decoding using the SMB0CN register. C8051F310/1/2/3/4/5/6/7 Rev. 1.7 153 ...
Page 154
... C8051F310/1/2/3/4/5/6/7 SFR Definition 14.2. SMB0CN: SMBus Control R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. Bit6: TXMODE: SMBus Transmit Mode Indicator. ...
Page 155
... ACK/NACK received. SI • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. C8051F310/1/2/3/4/5/6/7 Cleared by Hardware When... • A STOP is generated. • Arbitration is lost. • A START is detected. • Arbitration is lost. • SMB0DAT is not written before the start of an SMBus frame. • ...
Page 156
... C8051F310/1/2/3/4/5/6/7 14.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register ...
Page 157
... Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode. S SLA Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 14.5. Typical Master Transmitter Sequence C8051F310/1/2/3/4/5/6 Data Byte A Data Byte Interrupt Interrupt S = START P = STOP ...
Page 158
... C8051F310/1/2/3/4/5/6/7 14.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direc- tion bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to ‘ ...
Page 159
... Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. S SLA W Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 14.7. Typical Slave Receiver Sequence C8051F310/1/2/3/4/5/6/7 A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev ...
Page 160
... C8051F310/1/2/3/4/5/6/7 14.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set ...
Page 161
... ACK received. A master data byte was 1000 received; ACK requested. C8051F310/1/2/3/4/5/6/7 Typical Response Options Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT. End transfer with STOP. End transfer with STOP and start another transfer ...
Page 162
... C8051F310/1/2/3/4/5/6/7 Table 14.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted error detected. A STOP was detected while 0101 addressed Slave Transmit- ter. A slave address was ...
Page 163
... CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). Write to SBUF UART Baud Rate Generator Figure 15.1. UART0 Block Diagram C8051F310/1/2/3/4/5/6/7 164). Received data buffering allows SFR Bus TB8 SBUF SET (TX Shift) D ...
Page 164
... C8051F310/1/2/3/4/5/6/7 15.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 15.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. ...
Page 165
... RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK START D0 BIT SPACE BIT TIMES BIT SAMPLING Figure 15.4. 8-Bit UART Timing Diagram C8051F310/1/2/3/4/5/6/7 TX RS-232 RS-232 C8051Fxxx LEVEL RX XLTR OR TX ...
Page 166
... C8051F310/1/2/3/4/5/6/7 15.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg- ister PSW) for error detection, or used in multiprocessor communications ...
Page 167
... Master Device Device Figure 15.6. UART Multi-Processor Mode Interconnect Diagram C8051F310/1/2/3/4/5/6/7 Slave Slave Device Rev. 1.7 Slave Device ...
Page 168
... C8051F310/1/2/3/4/5/6/7 SFR Definition 15.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Bit6: UNUSED. Read = 1b. Write = don’ ...
Page 169
... This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmis- sion. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the con- tents of the receive latch. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W ...
Page 170
... C8051F310/1/2/3/4/5/6/7 Table 15.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% *Note: SCA1–SCA0 and T1M bit definitions can be found in Table 15 ...
Page 171
... SCA1–SCA0 and T1M bit definitions can be found in C8051F310/1/2/3/4/5/6/7 Timer Clock SCA1-SCA0 T1M* Source (pre-scale select)* SYSCLK XX SYSCLK XX SYSCLK XX SYSCLK / 12 00 SYSCLK / 12 00 SYSCLK / 12 ...
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... C8051F310/1/2/3/4/5/6/7 Table 15.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 0.00% 57600 0 ...
Page 173
... I/O pins can be used to select multiple slave devices in master mode. SPI0CKR Clock Divide SYSCLK Logic Transmit Data Buffer 7 6 Receive Data Buffer Write SPI0DAT SFR Bus Figure 16.1. SPI Block Diagram C8051F310/1/2/3/4/5/6/7 SFR Bus SPI0CFG SPI0CN SPI CONTROL LOGIC Data Path Pin Interface Control Control MOSI Tx Data SPI0DAT SCK ...
Page 174
... C8051F310/1/2/3/4/5/6/7 16.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 16.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat- ing as a master and an input when SPI0 is operating as a slave ...
Page 175
... SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 16.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. C8051F310/1/2/3/4/5/6/7 Rev. 1.7 175 ...
Page 176
... C8051F310/1/2/3/4/5/6/7 Master Device 1 Figure 16.2. Multiple-Master Mode Connection Diagram Master Device Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram 176 NSS GPIO MISO MISO Master MOSI ...
Page 177
... The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. C8051F310/1/2/3/4/5/6/7 Rev. 1.7 177 ...
Page 178
... C8051F310/1/2/3/4/5/6/7 16.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock ...
Page 179
... NSS (4-Wire Mode) Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 16.7. Slave Mode Data/Clock Timing (CKPHA = 1) C8051F310/1/2/3/4/5/6/7 Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 6 ...
Page 180
... C8051F310/1/2/3/4/5/6/7 16.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following register definitions ...
Page 181
... SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. Bit 0: SPIEN: SPI0 Enable. This bit enables/disables the SPI. 0: SPI disabled. 1: SPI enabled. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W TXBMT Bit4 Bit3 ...
Page 182
... C8051F310/1/2/3/4/5/6/7 SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7–0: SCR7–SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register ...
Page 183
... SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.9. SPI Master Timing (CKPHA = 1) C8051F310/1/2/3/4/5/6/7 T MCKL T T MIS MIH T MCKL T MIH Rev ...
Page 184
... C8051F310/1/2/3/4/5/6/7 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* T CKH T SIS MOSI T T SOH SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. ...
Page 185
... MOSI Valid to SCK Sample Edge SIS T SCK Sample Edge to MOSI Change SIH T SCK Shift Edge to MISO Change SOH Last SCK Edge to MISO Change T SLH (CKPHA = 1 ONLY) *Note equal to one period of the device system clock (SYSCLK). SYSCLK C8051F310/1/2/3/4/5/6/7 Min SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK — ...
Page 186
... C8051F310/1/2/3/4/5/6 OTES 186 Rev. 1.7 ...
Page 187
... As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled. C8051F310/1/2/3/4/5/6/7 Timer 2 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Rev ...
Page 188
... C8051F310/1/2/3/4/5/6/7 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “13.1. Priority Crossbar Decoder” on page 131 pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock ...
Page 189
... TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is active as defined by bit IN0PL in register IT01CF (see for details on the external input signals /INT0 and /INT1). Pre-scaled Clock SYSCLK T0 Crossbar GATE0 IN0PL XOR /INT0 Figure 17.2. T0 Mode 2 Block Diagram C8051F310/1/2/3/4/5/6/7 Section “8.3.2. External Interrupts” on page 95 CKCON TMOD INT01CF ...
Page 190
... C8051F310/1/2/3/4/5/6/7 17.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock ...
Page 191
... IT0: Interrupt 0 Type Select. This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 8.11). 0: /INT0 is level triggered. 1: /INT0 is edge triggered. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W R/W TR0 ...
Page 192
... C8051F310/1/2/3/4/5/6/7 SFR Definition 17.2. TMOD: Timer Mode R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in regis- ter IT01CF (see SFR Definition 8 ...
Page 193
... SCA1 SCA0 Note: External clock divided synchronized with the system clock, and the external clock must be less than or equal to the system clock to operate in this mode. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W T2ML T1M T0M SCA1 Bit4 Bit3 Bit2 Prescaled Clock System clock divided by 12 ...
Page 194
... C8051F310/1/2/3/4/5/6/7 SFR Definition 17.4. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 17.5. TL1: Timer 1 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7– ...
Page 195
... CKCON T2XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 17.4. Timer 2 16-Bit Mode Block Diagram C8051F310/1/2/3/4/5/6/7 To SMBus TMR2L Overflow TCLK TR2 TMR2L TMR2H TMR2RLL TMR2RLH Reload Rev. 1.7 To ADC, SMBus TF2H Interrupt TF2L TF2LEN T2SPLIT TR2 T2XCLK 195 ...
Page 196
... C8051F310/1/2/3/4/5/6/7 17.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 17.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control TMR2H. TMR2L is always running when configured for 8-bit Mode ...
Page 197
... Timer 2 external clock selection is the system clock divided by 12. 1: Timer 2 external clock selection is the external clock divided by 8. Note that the external oscillator source divided synchronized with the system clock. C8051F310/1/2/3/4/5/6/7 R/W R/W R/W ...
Page 198
... C8051F310/1/2/3/4/5/6/7 SFR Definition 17.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition 17.10. TMR2RLH: Timer 2 Reload Register High Byte ...
Page 199
... CKCON T3XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 17.6. Timer 3 16-Bit Mode Block Diagram C8051F310/1/2/3/4/5/6/7 TCLK TR3 TMR3L TMR3H TMR3RLL TMR3RLH Reload Rev. 1.7 To ADC TF3H Interrupt TF3L TF3LEN T3SPLIT TR3 T3XCLK 199 ...
Page 200
... C8051F310/1/2/3/4/5/6/7 17.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 17.5. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control TMR3H. TMR3L is always running when configured for 8-bit Mode ...