MC68HC711E9CFU2 Freescale Semiconductor, MC68HC711E9CFU2 Datasheet - Page 121

• Manufacturer Part Number: MC68HC711E9CFU2
• Description: IC MCU 12K OTP 2MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFU2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.5 SPI Signals
This subsection contains descriptions of the four SPI signals:
Any SPI output line must have its corresponding data direction bit in DDRD register set. If the DDR bit is
clear, that line is disconnected from the SPI logic and becomes a general-purpose input. All SPI input lines
are forced to act as inputs regardless of the state of the corresponding DDR bits in DDRD register.
8.5.1 Master In/Slave Out
MISO is one of two unidirectional serial data signals. It is an input to a master device and an output from
a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device
is not selected.
8.5.2 Master Out/Slave In
The MOSI line is the second of the two unidirectional serial data signals. It is an output from a master
device and an input to a slave device. The master device places data on the MOSI line a half-cycle before
the clock edge that the slave device uses to latch the data.
Freescale Semiconductor
1. SS ASSERTED
2. MASTER WRITES TO SPDR
3. FIRST SCK EDGE
4. SPIF SET
5. SS NEGATED
•
•
•
•
(CPHA = 0)
(CPHA = 1)
Master in/slave out (MISO)
Master out/slave in (MOSI)
Serial clock (SCK)
Slave select (SS)
SAMPLE INPUT
SAMPLE INPUT
SCK (CPOL = 0)
SCK (CPOL = 1)
SS (TO SLAVE)
SCK CYCLE #
DATA OUT
DATA OUT
1
2
MSB
3
MSB
1
M68HC11E Family Data Sheet, Rev. 5.1
Figure 8-2. SPI Transfer Format
6
2
6
SLAVE CPHA = 1 TRANSFER IN PROGRESS
SLAVE CPHA = 0 TRANSFER IN PROGRESS
5
MASTER TRANSFER IN PROGRESS
3
5
4
4
4
3
5
3
2
6
2
1
7
1
LSB
8
LSB
4
SPI Signals
5
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