MC68HC711E9CFU2

Manufacturer Part NumberMC68HC711E9CFU2
DescriptionIC MCU 12K OTP 2MHZ 64-QFP
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E9CFU2 datasheets
 

Specifications of MC68HC711E9CFU2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size12KB (12K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-QFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Operating Modes and On-Chip Memory
0
0
IRV(NE) — Internal Read Visibility (Not E) Bit
IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV is on
or off. In special test mode, IRVNE is reset to 1. In all other modes, IRVNE is reset to 0. For the
MC68HC811E2, this bit is IRV and only controls the internal read visibility function.
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
In single-chip modes this bit determines whether the E clock drives out from the chip. For the
MC68HC811E2, this bit has no meaning or effect in single-chip and bootstrap modes.
0 = E is driven out from the chip.
1 = E pin is driven low. Refer to the following table.
Mode
Single chip
Expanded
Bootstrap
Special test
PSEL[3:0] — Priority Select Bits
Refer to
Chapter 5 Resets and
2.3.3 System Initialization
Registers and bits that control initialization and the basic operation of the MCU are protected against
writes except under special circumstances.
reset or that must be written within the first 64 cycles after reset.
Table 2-2. Write Access Limited Registers
Operating
Register
Mode
Address
SMOD = 0
$x024
Timer interrupt mask 2 (TMSK2)
$x035
Block protect register (BPROT)
$x039
System configuration options (OPTION)
Highest priority I-bit interrupt
$x03C
and miscellaneous (HPRIO)
$x03D
RAM and I/O map register (INIT)
SMOD = 1
$x024
Timer interrupt mask 2 (TMSK2)
$x035
Block protect register (BPROT)
$x039
System configuration options (OPTION)
Highest priority I-bit interrupt and
$x03C
miscellaneous (HPRIO)
$x03D
RAM and I/O map register (INIT)
42
0
Bootstrap
1
Special test
IRVNE Out
E Clock Out
of Reset
of Reset
0
On
0
On
0
On
1
On
Interrupts.
Table 2-2
lists registers that can be written only once after
Register Name
in First 64 Cycles
Bits [1:0], once only
Clear bits, once only
Bits [5:4], bits [2:0], once only
See HPRIO description
Yes, once only
See HPRIO description
M68HC11E Family Data Sheet, Rev. 5.1
1
0
1
1
IRV Out
IRVNE
of Reset
Affects Only
Off
E
Off
IRV
Off
E
On
IRV
Must be Written
Write
Anytime
Bits [7:2]
Set bits only
Bits [7:6], bit 3
See HPRIO description
All, set or clear
All, set or clear
All, set or clear
See HPRIO description
All, set or clear
Freescale Semiconductor
IRVNE Can
Be Written
Once
Once
Once
Once