MC68HC711E9CFU2

Manufacturer Part NumberMC68HC711E9CFU2
DescriptionIC MCU 12K OTP 2MHZ 64-QFP
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E9CFU2 datasheets
 

Specifications of MC68HC711E9CFU2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size12KB (12K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-QFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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5.2.6 Configuration Control Register
Address:
$103F
Bit 7
Read:
EE3
Write:
Reset:
0
Figure 5-3. Configuration Control Register (CONFIG)
EE[3:0] — EEPROM Mapping Bits
EE[3:0] apply only to MC68HC811E2. Refer to
NOSEC — Security Mode Disable Bit
Refer to
Chapter 2 Operating Modes and On-Chip
NOCOP — COP System Disable Bit
0 = COP enabled (forces reset on timeout)
1 = COP disabled (does not force reset on timeout)
ROMON — ROM (EPROM) Enable Bit
Refer to
Chapter 2 Operating Modes and On-Chip
EEON — EEPROM Enable Bit
Refer to
Chapter 2 Operating Modes and On-Chip
5.3 Effects of Reset
When a reset condition is recognized, the internal registers and control bits are forced to an initial state.
Depending on the cause of the reset and the operating mode, the reset vector can be fetched from any
of six possible locations. Refer to
Table 5-2. Reset Cause, Reset Vector, and Operating Mode
Cause of Reset
POR or RESET pin
Clock monitor failure
COP Watchdog Timeout
These initial states then control on-chip peripheral systems to force them to known startup states, as
described in the following subsections.
5.3.1 Central Processor Unit (CPU)
After reset, the central processor unit (CPU) fetches the restart vector from the appropriate address during
the first three cycles and begins executing instructions. The stack pointer and other CPU registers are
indeterminate immediately after reset; however, the X and I interrupt mask bits in the condition code
register (CCR) are set to mask any interrupt requests. Also, the S bit in the CCR is set to inhibit stop mode.
Freescale Semiconductor
6
5
4
3
EE2
EE1
EE0
NOSEC
0
0
0
1
Chapter 2 Operating Modes and On-Chip
Memory.
Memory.
Memory.
Table
5-2.
Normal Mode
Vector
$FFFE, FFFF
$FFFC, FFFD
$FFFA, FFFB
M68HC11E Family Data Sheet, Rev. 5.1
Effects of Reset
2
1
Bit 0
NOCOP
ROMON
EEON
1
1
1
Memory.
Special Test
or Bootstrap
$BFFE, $BFFF
$BFFC, $BFFD
$BFFA, $BFFB
83