MC68HC711E9VFN2 Freescale Semiconductor, MC68HC711E9VFN2 Datasheet - Page 102

• Manufacturer Part Number: MC68HC711E9VFN2
• Description: IC MCU 12K OTP 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9VFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.8 Parallel I/O Control Register
The parallel handshake functions are available only in the single-chip operating mode. PIOC is a
read/write register except for bit 7, which is read only.
operations.
STAF — Strobe A Interrupt Status Flag
STAI — Strobe A Interrupt Enable Mask Bit
102
Simple
strobed
mode
Full-input
hand-
shake
mode
Full-
output
hand-
shake
mode
Parallel Input/Output (I/O) Ports
STAF is set when the selected edge occurs on strobe A. This bit can be cleared by a read of PIOC with
STAF set followed by a read of PORTCL (simple strobed or full input handshake mode) or a write to
PORTCL (output handshake mode).
0 = No edge on strobe A
1 = Selected edge on strobe A
0 = STAF does not request interrupt
1 = STAF requests interrupt
Read
PIOC with
STAF = 1
then read
PORTCL
Read
PIOC with
STAF = 1
then read
PORTCL
Read
PIOC with
STAF = 1
then write
PORTCL
Sequence
Clearing
STAF
Address:
Reset:
Read:
Write:
HNDS
U = Unaffected
$1002
Figure 6-10. Parallel I/O Control Register (PIOC)
STAF
0
1
1
Bit 7
0
OIN
X
0
1
M68HC11E Family Data Sheet, Rev. 5.1
STAI
Table 6-2. Parallel I/O Control
6
0
0 = STRB
active level
1 = STRB
active pulse
0 = STRB
active level
1 = STRB
active pulse
PLS
X
CWOM
5
0
Follow
DDRC
HNDS
0
1
1
0
0
1
Table 6-2
4
0
Active Edge
Port C
Driven
EGA
STRA
OIN
3
0
shows a summary of handshake
Follow
DDRC
PLS
U
2
Inputs latched into
PORTCL on any
active edge on
STRA
Inputs latched into
PORTCL on any
active edge on
STRA
Driven as outputs if
STRA at active
level; follows
DDRC
if STRA not at
active level
Port B
EGA
1
1
Freescale Semiconductor
INVB
Bit 0
STRB pulses
on writes
to PORTB
Normal output
port, unaffected
in handshake
modes
Normal output
port, unaffected
in handshake
modes
1
Port C