MC68HC711K4CFN4 Freescale Semiconductor, MC68HC711K4CFN4 Datasheet - Page 211

• Manufacturer Part Number: MC68HC711K4CFN4
• Description: IC MCU 24K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.9 Pulse-Width Modulator (PWM)
9.9.1 PWM System Description
M68HC11K Family
MOTOROLA
Four 8-bit pulse-width modulation channels are available in the
M68HC11K Family devices. They are output on port H pins 3–0. Pairs of
channels can be concatenated to produce 16-bit outputs. Three
programmable clocks and a flexible clock selection scheme provide a
wide range of frequencies.
The 8-bit mode with E = 4 MHz can produce waveforms from 40 kHz at
1 percent duty cycle resolution to less than 10 Hz at 0.4 percent duty
cycle resolution. In 16-bit mode, a duty cycle resolution down to 15 parts
per million can be achieved (at a frequency of 60 Hz). At 1 kHz, the duty
cycle resolution is 250 ppm.
Figure 9-30
channels is enabled by bit PWENx in the PWEN register. Each channel
has an 8-bit counter (PWCNTx), a period register (PWPERx), and a duty
cycle register (PWDTYx). The counter is driven by one of three
user-scaled clock sources — clock A, B, or S — selected by the
pulse-width channel select (PCLKx) bit in the pulse-width modulation
timer polarity (PWPOL) register.
A pulse-width modulation period begins when the counter matches the
value stored in the period register. When this happens, a logic value
determined by the polarity bit (PPOLx) in the PWPOL register is driven
on the associated port H output pin, and the counter is reset to 0. When
the counter matches the number stored in the duty cycle register, the
output reverses polarity. The period and duty cycle registers are double
buffered so they can be changed without disturbing the current
waveform. A new period or duty cycle can be forced by writing to the
period (PWPERx) or duty cycle register (PWDTYx) and then to the
counter (PWCNTx). Writing to the counter always resets it to 0.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
shows a block diagram of the PWM system. Each of four
Timing System
Pulse-Width Modulator (PWM)
Timing System
Technical Data
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